From 8561c8366c7c9afd7e6b52b6e2385b3c1dde95a9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 25 Jan 2007 13:43:46 -0500 Subject: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back --HG-- extra : convert_revision : 50a23837fd888393a5c2aa35cbd1abeebb7f55d4 --- src/cpu/simple/base.cc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ddccc5a9b..14fefe103 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -439,6 +439,8 @@ BaseSimpleCPU::advancePC(Fault fault) if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); + thread->setMicroPC(0); + thread->setNextMicroPC(1); } else { //If we're at the last micro op for this instruction if (curStaticInst->isLastMicroOp()) { -- cgit v1.2.3 From 202d7f62b9ea11e6b72c4b15ff818549ea14f038 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Fri, 26 Jan 2007 12:51:07 -0500 Subject: eliminate cpu checkInterrupts bool, it is redundant and unnecessary. --HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719 --- src/cpu/base.cc | 4 +--- src/cpu/base.hh | 1 - src/cpu/o3/alpha/cpu_impl.hh | 3 --- src/cpu/o3/commit_impl.hh | 3 +-- src/cpu/o3/sparc/cpu_impl.hh | 1 - src/cpu/ozone/cpu_impl.hh | 7 ------- src/cpu/ozone/inorder_back_end_impl.hh | 4 +--- src/cpu/simple/base.cc | 3 +-- 8 files changed, 4 insertions(+), 22 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index b03bc19a5..deb4e02c4 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -96,7 +96,7 @@ CPUProgressEvent::description() #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) - : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true), + : MemObject(p->name), clock(p->clock), instCnt(0), params(p), number_of_threads(p->numberOfThreads), system(p->system), phase(p->phase) #else @@ -334,7 +334,6 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) #if FULL_SYSTEM interrupts = oldCPU->interrupts; - checkInterrupts = oldCPU->checkInterrupts; for (int i = 0; i < threadContexts.size(); ++i) threadContexts[i]->profileClear(); @@ -371,7 +370,6 @@ BaseCPU::post_interrupt(int int_type) void BaseCPU::post_interrupt(int int_num, int index) { - checkInterrupts = true; interrupts.post(int_num, index); } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 89c7d9dda..3ae9c60b6 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -106,7 +106,6 @@ class BaseCPU : public MemObject virtual void post_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupts(); - bool checkInterrupts; bool check_interrupts(ThreadContext * tc) const { return interrupts.check_interrupts(tc); } diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 98fd0699a..980e70fdd 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -217,8 +217,6 @@ AlphaO3CPU::hwrei(unsigned tid) this->thread[tid]->kernelStats->hwrei(); - this->checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -270,7 +268,6 @@ AlphaO3CPU::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 96f094926..483c2f71b 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -671,8 +671,7 @@ DefaultCommit::commit() } else { DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); } - } else if (cpu->checkInterrupts && - cpu->check_interrupts(cpu->tcBase(0)) && + } else if (cpu->check_interrupts(cpu->tcBase(0)) && commitStatus[0] != TrapPending && !trapSquash[0] && !tcSquash[0]) { diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh index 536a620bf..66bf7d1c0 100644 --- a/src/cpu/o3/sparc/cpu_impl.hh +++ b/src/cpu/o3/sparc/cpu_impl.hh @@ -245,7 +245,6 @@ SparcO3CPU::processInterrupts(Fault interrupt) this->interrupts.updateIntrInfo(this->threadContexts[0]); DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name()); - this->checkInterrupts = false; this->trap(interrupt, 0); } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index accc8d294..a854de8de 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -182,10 +182,6 @@ OzoneCPU::OzoneCPU(Params *p) globalSeqNum = 1; -#if FULL_SYSTEM - checkInterrupts = false; -#endif - lockFlag = 0; // Setup rename table, initializing all values to ready. @@ -684,8 +680,6 @@ OzoneCPU::hwrei() lockAddrList.clear(); thread.kernelStats->hwrei(); - checkInterrupts = true; - // FIXME: XXX check for interrupts? XXX return NoFault; } @@ -704,7 +698,6 @@ OzoneCPU::processInterrupts() if (interrupt != NoFault) { this->interrupts.updateIntrInfo(thread.getTC()); - this->checkInterrupts = false; interrupt->invoke(thread.getTC()); } } diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 87bf0a7a2..84f935a72 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -88,7 +88,6 @@ InorderBackEnd::checkInterrupts() int ipl = 0; int summary = 0; - cpu->checkInterrupts = false; if (thread->readMiscReg(IPR_ASTRR)) panic("asynchronous traps not implemented\n"); @@ -151,8 +150,7 @@ InorderBackEnd::tick() // I'm waiting for it to drain. (for now just squash) #if FULL_SYSTEM if (interruptBlocked || - (cpu->checkInterrupts && - cpu->check_interrupts(tc))) { + cpu->check_interrupts(tc)) { if (!robEmpty()) { interruptBlocked = true; //AlphaDep diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index ddccc5a9b..9e5dfe2a6 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -311,12 +311,11 @@ void BaseSimpleCPU::checkForInterrupts() { #if FULL_SYSTEM - if (checkInterrupts && check_interrupts(tc)) { + if (check_interrupts(tc)) { Fault interrupt = interrupts.getInterrupt(tc); if (interrupt != NoFault) { interrupts.updateIntrInfo(tc); - checkInterrupts = false; interrupt->invoke(tc); } } -- cgit v1.2.3 From 63fdabf191b8ac1031fb25da61ab2526d4bb6d05 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:48:51 -0500 Subject: make our code a little more standards compliant pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd --- src/cpu/SConscript | 8 ++++---- src/cpu/activity.cc | 6 ++++-- src/cpu/exetrace.hh | 3 ++- src/cpu/simple/base.hh | 3 ++- 4 files changed, 12 insertions(+), 8 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 5771a7904..4d4b7574c 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -54,18 +54,18 @@ execfile(models_db.srcnode().abspath) exec_sig_template = ''' virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const -{ panic("initiateAcc not defined!"); }; +{ panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; virtual Fault completeAcc(Packet *pkt, %s *xc, Trace::InstRecord *traceData) const -{ panic("completeAcc not defined!"); }; +{ panic("completeAcc not defined!"); M5_DUMMY_RETURN }; ''' mem_ini_sig_template = ''' -virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); }; +virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); M5_DUMMY_RETURN }; ''' mem_comp_sig_template = ''' -virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; }; +virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) const { panic("Not defined!"); return NoFault; M5_DUMMY_RETURN }; ''' # Generate a temporary CPU list, including the CheckerCPU if diff --git a/src/cpu/activity.cc b/src/cpu/activity.cc index 9a0f6d98d..15e0556ad 100644 --- a/src/cpu/activity.cc +++ b/src/cpu/activity.cc @@ -28,6 +28,8 @@ * Authors: Kevin Lim */ +#include + #include "base/timebuf.hh" #include "cpu/activity.hh" @@ -37,7 +39,7 @@ ActivityRecorder::ActivityRecorder(int num_stages, int longest_latency, activityCount(activity), numStages(num_stages) { stageActive = new bool[numStages]; - memset(stageActive, 0, numStages); + std::memset(stageActive, 0, numStages); } void @@ -114,7 +116,7 @@ void ActivityRecorder::reset() { activityCount = 0; - memset(stageActive, 0, numStages); + std::memset(stageActive, 0, numStages); for (int i = 0; i < longestLatency + 1; ++i) activityBuffer.advance(); } diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index 6562e5265..a825f6a82 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -32,6 +32,7 @@ #ifndef __EXETRACE_HH__ #define __EXETRACE_HH__ +#include #include #include @@ -169,7 +170,7 @@ InstRecord::setRegs(const IntRegFile ®s) if (!iregs) iregs = new iRegFile; - memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); + std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile)); regs_valid = true; } diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index c39bfa9cd..31fd00977 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -186,7 +186,8 @@ class BaseSimpleCPU : public BaseCPU // These functions are only used in CPU models that split // effective address computation from the actual memory access. void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } - Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); } + Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); + M5_DUMMY_RETURN} void prefetch(Addr addr, unsigned flags) { -- cgit v1.2.3 From 2939d7d061efc8444c06ac52f82c8aeaf0048aaf Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 26 Jan 2007 18:57:16 -0500 Subject: Make Sparc traceflag even more chatty some fixes to fp instructions to use the single precision registers if this is an fp op emit fp check code add fpregs to m5legion struct src/arch/sparc/floatregfile.cc: Make Sparc traceflag even more chatty src/arch/sparc/isa/base.isa: add code to check if the fpu is enabled src/arch/sparc/isa/decoder.isa: some fixes to fp instructions to use the single precision registers fix smul again fix subc/subcc/subccc condition code setting src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/mem/util.isa: if this is an fp op emit fp check code src/cpu/exetrace.cc: check fp regs as well as int regs src/cpu/m5legion_interface.h: add fpregs to m5legion struct --HG-- extra : convert_revision : e7d26d10fb8ce88f96e3a51f84b48c3b3ad2f232 --- src/cpu/exetrace.cc | 54 ++++++++++++++++++++++++-------------------- src/cpu/m5legion_interface.h | 5 ++-- 2 files changed, 32 insertions(+), 27 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 26e8b6b44..9ea90681c 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -293,7 +293,8 @@ Trace::InstRecord::dump(ostream &outs) bool diffPC = false; bool diffCC = false; bool diffInst = false; - bool diffRegs = false; + bool diffIntRegs = false; + bool diffFpRegs = false; bool diffTpc = false; bool diffTnpc = false; bool diffTstate = false; @@ -357,10 +358,15 @@ Trace::InstRecord::dump(ostream &outs) } for (int i = 0; i < TheISA::NumIntArchRegs; i++) { if (thread->readIntReg(i) != shared_data->intregs[i]) { - diffRegs = true; + diffIntRegs = true; } } - uint64_t oldTl = thread->readMiscReg(MISCREG_TL); + for (int i = 0; i < TheISA::NumFloatRegs/2; i++) { + if (thread->readFloatRegBits(i,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) { + diffFpRegs = true; + } + } + uint64_t oldTl = thread->readMiscReg(MISCREG_TL); if (oldTl != shared_data->tl) diffTl = true; for (int i = 1; i <= MaxTL; i++) { @@ -426,12 +432,12 @@ Trace::InstRecord::dump(ostream &outs) diffTlb = true; } - if ((diffPC || diffCC || diffInst || diffRegs || diffTpc || - diffTnpc || diffTstate || diffTt || diffHpstate || - diffHtstate || diffHtba || diffPstate || diffY || - diffCcr || diffTl || diffGl || diffAsi || diffPil || - diffCwp || diffCansave || diffCanrestore || - diffOtherwin || diffCleanwin || diffTlb) + if ((diffPC || diffCC || diffInst || diffIntRegs || + diffFpRegs || diffTpc || diffTnpc || diffTstate || + diffTt || diffHpstate || diffHtstate || diffHtba || + diffPstate || diffY || diffCcr || diffTl || diffGl || + diffAsi || diffPil || diffCwp || diffCansave || + diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) @@ -444,8 +450,10 @@ Trace::InstRecord::dump(ostream &outs) outs << " [CC]"; if (diffInst) outs << " [Instruction]"; - if (diffRegs) + if (diffIntRegs) outs << " [IntRegs]"; + if (diffFpRegs) + outs << " [FpRegs]"; if (diffTpc) outs << " [Tpc]"; if (diffTnpc) @@ -588,26 +596,22 @@ Trace::InstRecord::dump(ostream &outs) printSectionHeader(outs, "General Purpose Registers"); static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; - for(int y = 0; y < 4; y++) - { - for(int x = 0; x < 8; x++) - { + for(int y = 0; y < 4; y++) { + for(int x = 0; x < 8; x++) { char label[8]; sprintf(label, "%s%d", regtypes[y], x); printRegPair(outs, label, thread->readIntReg(y*8+x), shared_data->intregs[y*8+x]); - /*outs << regtypes[y] << x << " " ; - outs << "0x" << hex << setw(16) - << thread->readIntReg(y*8+x); - if (thread->readIntReg(y*8 + x) - != shared_data->intregs[y*8+x]) - outs << " X "; - else - outs << " | "; - outs << "0x" << setw(16) << hex - << shared_data->intregs[y*8+x] - << endl;*/ + } + } + if (diffFpRegs) { + for (int x = 0; x < 32; x++) { + char label[8]; + sprintf(label, "%%f%d", x); + printRegPair(outs, label, + thread->readFloatRegBits(x,FloatRegFile::DoubleWidth), + shared_data->fpregs[x]); } } if (diffTlb) { diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index c3ba5986e..81714f769 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006 The Regents of The University of Michigan + * Copyright (c) 2006-2007 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -30,7 +30,7 @@ #include -#define VERSION 0xA1000007 +#define VERSION 0xA1000008 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -47,6 +47,7 @@ typedef struct { uint32_t instruction; uint32_t new_instruction; uint64_t intregs[32]; + uint64_t fpregs[32]; uint64_t tpc[8]; uint64_t tnpc[8]; -- cgit v1.2.3