From 0be64ffe2f4ff8824b3084362706ffbf456ea490 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 31 May 2014 18:00:23 -0700 Subject: style: eliminate equality tests with true and false Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'. It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up. Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code. --- src/cpu/exetrace.cc | 2 +- src/cpu/inorder/cpu.cc | 2 +- src/cpu/inorder/pipeline_stage.cc | 6 +++--- src/cpu/inorder/resources/use_def.cc | 2 +- src/cpu/o3/commit_impl.hh | 6 +++--- src/cpu/o3/fetch_impl.hh | 4 ++-- src/cpu/o3/iew_impl.hh | 10 +++++----- src/cpu/o3/inst_queue_impl.hh | 2 +- src/cpu/o3/lsq_unit_impl.hh | 8 ++++---- src/cpu/o3/rob_impl.hh | 2 +- src/cpu/ozone/inst_queue_impl.hh | 2 +- 11 files changed, 23 insertions(+), 23 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 2877db187..b3b6e6a60 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -115,7 +115,7 @@ Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) outs << Enums::OpClassStrings[inst->opClass()] << " : "; } - if (Debug::ExecResult && predicate == false) { + if (Debug::ExecResult && !predicate) { outs << "Predicated False"; } diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index eecbd033e..e966e8e83 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -1763,7 +1763,7 @@ InOrderCPU::cleanUpRemovedInsts() // Clear if Non-Speculative if (inst->staticInst && inst->seqNum == nonSpecSeqNum[tid] && - nonSpecInstActive[tid] == true) { + nonSpecInstActive[tid]) { nonSpecInstActive[tid] = false; } diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc index d98fbb744..5e94c665f 100644 --- a/src/cpu/inorder/pipeline_stage.cc +++ b/src/cpu/inorder/pipeline_stage.cc @@ -248,19 +248,19 @@ void PipelineStage::removeStalls(ThreadID tid) { for (int st_num = 0; st_num < NumStages; st_num++) { - if (stalls[tid].stage[st_num] == true) { + if (stalls[tid].stage[st_num]) { DPRINTF(InOrderStage, "Removing stall from stage %i.\n", st_num); stalls[tid].stage[st_num] = false; } - if (toPrevStages->stageBlock[st_num][tid] == true) { + if (toPrevStages->stageBlock[st_num][tid]) { DPRINTF(InOrderStage, "Removing pending block from stage %i.\n", st_num); toPrevStages->stageBlock[st_num][tid] = false; } - if (fromNextStages->stageBlock[st_num][tid] == true) { + if (fromNextStages->stageBlock[st_num][tid]) { DPRINTF(InOrderStage, "Removing pending block from stage %i.\n", st_num); fromNextStages->stageBlock[st_num][tid] = false; diff --git a/src/cpu/inorder/resources/use_def.cc b/src/cpu/inorder/resources/use_def.cc index d25925b9b..5a871d0d4 100644 --- a/src/cpu/inorder/resources/use_def.cc +++ b/src/cpu/inorder/resources/use_def.cc @@ -191,7 +191,7 @@ UseDefUnit::execute(int slot_idx) // If there is a non-speculative instruction // in the pipeline then stall instructions here // --- - if (*nonSpecInstActive[tid] == true && seq_num > *nonSpecSeqNum[tid]) { + if (*nonSpecInstActive[tid] && seq_num > *nonSpecSeqNum[tid]) { DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because" "there is non-speculative instruction [sn:%i] has not " "graduated.\n", tid, seq_num, *nonSpecSeqNum[tid]); diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 333687c84..b6fdc40bb 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -843,10 +843,10 @@ DefaultCommit::commit() // Not sure which one takes priority. I think if we have // both, that's a bad sign. - if (trapSquash[tid] == true) { + if (trapSquash[tid]) { assert(!tcSquash[tid]); squashFromTrap(tid); - } else if (tcSquash[tid] == true) { + } else if (tcSquash[tid]) { assert(commitStatus[tid] != TrapPending); squashFromTC(tid); } else if (commitStatus[tid] == SquashAfterPending) { @@ -885,7 +885,7 @@ DefaultCommit::commit() // then use one older sequence number. InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; - if (fromIEW->includeSquashInst[tid] == true) { + if (fromIEW->includeSquashInst[tid]) { squashed_inst--; } diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index a81125da6..93dc2e250 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -430,8 +430,8 @@ DefaultFetch::drainSanityCheck() const assert(isDrained()); assert(retryPkt == NULL); assert(retryTid == InvalidThreadID); - assert(cacheBlocked == false); - assert(interruptPending == false); + assert(!cacheBlocked); + assert(!interruptPending); for (ThreadID i = 0; i < numThreads; ++i) { assert(!memReq[i]); diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 3c133ff0c..644366dfc 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -487,7 +487,7 @@ DefaultIEW::squashDueToBranch(DynInstPtr &inst, ThreadID tid) DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum < toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; toCommit->squashedSeqNum[tid] = inst->seqNum; @@ -517,7 +517,7 @@ DefaultIEW::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) // case the memory violator should take precedence over the branch // misprediction because it requires the violator itself to be included in // the squash. - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum <= toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; @@ -538,7 +538,7 @@ DefaultIEW::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) { DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); - if (toCommit->squash[tid] == false || + if (!toCommit->squash[tid] || inst->seqNum < toCommit->squashedSeqNum[tid]) { toCommit->squash[tid] = true; @@ -1314,7 +1314,7 @@ DefaultIEW::executeInsts() } // If the store had a fault then it may not have a mem req - if (fault != NoFault || inst->readPredicate() == false || + if (fault != NoFault || !inst->readPredicate() || !inst->isStoreConditional()) { // If the instruction faulted, then we need to send it along // to commit without the instruction completing. @@ -1339,7 +1339,7 @@ DefaultIEW::executeInsts() // will be replaced and we will lose it. if (inst->getFault() == NoFault) { inst->execute(); - if (inst->readPredicate() == false) + if (!inst->readPredicate()) inst->forwardOldRegs(); } diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 8eba028d6..ab3861add 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -1262,7 +1262,7 @@ InstructionQueue::addToDependents(DynInstPtr &new_inst) // it be added to the dependency graph. if (src_reg >= numPhysRegs) { continue; - } else if (regScoreboard[src_reg] == false) { + } else if (!regScoreboard[src_reg]) { DPRINTF(IQ, "Instruction PC %s has src reg %i that " "is being added to the dependency chain.\n", new_inst->pcState(), src_reg); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 416f3e7e7..547800b4c 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -612,12 +612,12 @@ LSQUnit::executeLoad(DynInstPtr &inst) // If the instruction faulted or predicated false, then we need to send it // along to commit without the instruction completing. - if (load_fault != NoFault || inst->readPredicate() == false) { + if (load_fault != NoFault || !inst->readPredicate()) { // Send this instruction to commit, also make sure iew stage // realizes there is activity. // Mark it as executed unless it is an uncached load that // needs to hit the head of commit. - if (inst->readPredicate() == false) + if (!inst->readPredicate()) inst->forwardOldRegs(); DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", inst->seqNum, @@ -665,7 +665,7 @@ LSQUnit::executeStore(DynInstPtr &store_inst) store_fault == NoFault) return store_fault; - if (store_inst->readPredicate() == false) + if (!store_inst->readPredicate()) store_inst->forwardOldRegs(); if (storeQueue[store_idx].size == 0) { @@ -673,7 +673,7 @@ LSQUnit::executeStore(DynInstPtr &store_inst) store_inst->pcState(), store_inst->seqNum); return store_fault; - } else if (store_inst->readPredicate() == false) { + } else if (!store_inst->readPredicate()) { DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", store_inst->seqNum); return store_fault; diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh index 61d6bd11b..5a9dc90f9 100644 --- a/src/cpu/o3/rob_impl.hh +++ b/src/cpu/o3/rob_impl.hh @@ -519,7 +519,7 @@ ROB::readHeadInst(ThreadID tid) if (threadEntries[tid] != 0) { InstIt head_thread = instList[tid].begin(); - assert((*head_thread)->isInROB()==true); + assert((*head_thread)->isInROB()); return *head_thread; } else { diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh index babee399d..6e85464e2 100644 --- a/src/cpu/ozone/inst_queue_impl.hh +++ b/src/cpu/ozone/inst_queue_impl.hh @@ -1101,7 +1101,7 @@ InstQueue::addToDependents(DynInstPtr &new_inst) // it be added to the dependency graph. if (src_reg >= numPhysRegs) { continue; - } else if (regScoreboard[src_reg] == false) { + } else if (!regScoreboard[src_reg]) { DPRINTF(IQ, "Instruction PC %#x has src reg %i that " "is being added to the dependency chain.\n", new_inst->readPC(), src_reg); -- cgit v1.2.3