From 0db95030fc75792de8231bad7e66a09561eaa2ec Mon Sep 17 00:00:00 2001
From: Mrinmoy Ghosh <Mrinmoy.Ghosh@arm.com>
Date: Fri, 19 Aug 2011 15:08:05 -0500
Subject: LSQ: Fix a few issues with the storeset predictor.

Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
   the barrier was squashed instead of committed. This made all load insts
   dependent on a non-existent barrier in-flight.
---
 src/cpu/o3/mem_dep_unit_impl.hh | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index 6f3c922a7..bb4264a92 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -405,15 +405,14 @@ MemDepUnit<MemDepPred, Impl>::completeBarrier(DynInstPtr &inst)
     completed(inst);
 
     InstSeqNum barr_sn = inst->seqNum;
-
+    DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
+            inst->seqNum);
     if (inst->isMemBarrier()) {
-        assert(loadBarrier && storeBarrier);
         if (loadBarrierSN == barr_sn)
             loadBarrier = false;
         if (storeBarrierSN == barr_sn)
             storeBarrier = false;
     } else if (inst->isWriteBarrier()) {
-        assert(storeBarrier);
         if (storeBarrierSN == barr_sn)
             storeBarrier = false;
     }
@@ -480,6 +479,12 @@ MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
         DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
                 (*squash_it)->seqNum);
 
+        if ((*squash_it)->seqNum == loadBarrierSN)
+              loadBarrier = false;
+
+        if ((*squash_it)->seqNum == storeBarrierSN)
+              storeBarrier = false;
+
         hash_it = memDepHash.find((*squash_it)->seqNum);
 
         assert(hash_it != memDepHash.end());
@@ -509,7 +514,7 @@ MemDepUnit<MemDepPred, Impl>::violation(DynInstPtr &store_inst,
             " load: %#x, store: %#x\n", violating_load->instAddr(),
             store_inst->instAddr());
     // Tell the memory dependence unit of the violation.
-    depPred.violation(violating_load->instAddr(), store_inst->instAddr());
+    depPred.violation(store_inst->instAddr(), violating_load->instAddr());
 }
 
 template <class MemDepPred, class Impl>
-- 
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