From 1048b548fabfb7af2113f226f2151d3eb0e63289 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 18:06:57 -0800 Subject: X86: Separate out the page table walker into it's own cc and hh. --HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042 --- src/cpu/BaseCPU.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index cb5793e57..9fc1db9f1 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -101,9 +101,7 @@ class BaseCPU(SimObject): _mem_ports = [] if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - itb.walker_port = Port("ITB page table walker port") - dtb.walker_port = Port("ITB page table walker port") - _mem_ports = ["itb.walker_port", "dtb.walker_port"] + _mem_ports = ["itb.walker.port", "dtb.walker.port"] def connectMemPorts(self, bus): for p in self._mem_ports: -- cgit v1.2.3