From e9a395c2ce35bb0b46389ea3d73655e0bc824944 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Wed, 3 Jan 2007 10:13:45 -0800 Subject: Formatting --HG-- extra : convert_revision : bf1eae73995f772a4343c8ebcb254818eeb5d949 --- src/cpu/cpuevent.hh | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh index 3339f8252..c973621c0 100644 --- a/src/cpu/cpuevent.hh +++ b/src/cpu/cpuevent.hh @@ -36,12 +36,14 @@ class ThreadContext; -/** This class creates a global list of events that need a pointer to a - * thread context. When a switchover takes place the events can be migrated - * to the new thread context, otherwise you could have a wake timer interrupt - * go off on a switched out cpu or other unfortunate events. This object MUST be - * dynamically allocated to avoid it being deleted after a cpu switch happens. - * */ +/** + * This class creates a global list of events that need a pointer to a + * thread context. When a switchover takes place the events can be + * migrated to the new thread context, otherwise you could have a wake + * timer interrupt go off on a switched out cpu or other unfortunate + * events. This object MUST be dynamically allocated to avoid it being + * deleted after a cpu switch happens. + */ class CpuEvent : public Event { protected: @@ -78,8 +80,8 @@ class CpuEventWrapper : public CpuEvent T *object; public: - CpuEventWrapper(T *obj, ThreadContext *_tc, EventQueue *q = &mainEventQueue, - Priority p = Default_Pri) + CpuEventWrapper(T *obj, ThreadContext *_tc, + EventQueue *q = &mainEventQueue, Priority p = Default_Pri) : CpuEvent(q, _tc, p), object(obj) { } void process() { (object->*F)(tc); } -- cgit v1.2.3 From a8b2d66661e4be7cf5d5856f75f3f0e7849c5a9f Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 8 Jan 2007 17:11:10 -0500 Subject: change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early. --HG-- extra : convert_revision : f237363eababb2aad67e5b41670cf40be048a042 --- src/cpu/exetrace.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 352a11958..6e0bf6d33 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -609,7 +609,8 @@ Trace::InstRecord::dump(ostream &outs) diffcount++; if (diffcount > 2) fatal("Differences found between Legion and M5\n"); - } + } else + diffcount = 0; compared = true; shared_data->flags = OWN_LEGION; -- cgit v1.2.3 From 032ea9b2db870ad9b2a039f8c4020e38f5dd7f62 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Mon, 8 Jan 2007 18:18:28 -0500 Subject: the way i understand it, interrupts in m5 is a little bloated. the usage of CPU->checkInterrupts bool is inconsistent, and i think should eventually be phased out. For now, I've just assumed that CPU->checkInterrupts() is the way to fast path a CPU if you have no interrupts by having a simple bitfield in each ISA to determine whether interrupts are pending. getInterrupts has been mostly filled in. src/arch/sparc/interrupts.hh: fill in how we do interrupts on sparc a little bit. 1) create a bitfield for interrupts, and check that in checkInterrupts() to fast path CPU. 2) fill in getInterrupts() a little bit. also, update the bitfield access to be HPSTATE::hpriv, etc. src/arch/sparc/ua2005.cc: 1) update formatting 2) change the way interrupts are done to use the new way to tickle the CPU. src/cpu/base.cc: src/cpu/base.hh: overload the post_interrupt function for SPARC interrupts - which are only denoted by a single int value. --HG-- extra : convert_revision : 9074a003eff37a40dcce78f56d20f6cbcc453eb5 --- src/cpu/base.cc | 6 ++++++ src/cpu/base.hh | 1 + 2 files changed, 7 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 31604ad58..b03bc19a5 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -362,6 +362,12 @@ BaseCPU::ProfileEvent::process() schedule(curTick + interval); } +void +BaseCPU::post_interrupt(int int_type) +{ + interrupts.post(int_type); +} + void BaseCPU::post_interrupt(int int_num, int index) { diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 8c6b079da..89c7d9dda 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -102,6 +102,7 @@ class BaseCPU : public MemObject TheISA::Interrupts interrupts; public: + virtual void post_interrupt(int int_type); virtual void post_interrupt(int int_num, int index); virtual void clear_interrupt(int int_num, int index); virtual void clear_interrupts(); -- cgit v1.2.3 From ecfd628ecd394f8e7df654ffc7c342d959e12e15 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:06:05 -0500 Subject: Modify ISA and staticInst to support a IsFirstMicroOp flag Increment instruction count on first micro-op instead of last src/arch/sparc/isa/decoder.isa: Implement a twin load for ASI_LDTX_P(0xe2) src/arch/sparc/isa/formats/mem/blockmem.isa: set the new flag IsFirstMicroOp when needed src/cpu/simple/atomic.cc: Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion) src/cpu/static_inst.hh: Add IsFirstMicroop flag to static insts --HG-- extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc --- src/cpu/simple/atomic.cc | 2 +- src/cpu/static_inst.hh | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 8db864153..3b3536e44 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -497,7 +497,7 @@ AtomicSimpleCPU::tick() // @todo remove me after debugging with legion done if (curStaticInst && (!curStaticInst->isMicroOp() || - curStaticInst->isLastMicroOp())) + curStaticInst->isFirstMicroOp())) instCnt++; if (simulate_stalls) { diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index 523cfae40..5928eea76 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -146,6 +146,7 @@ class StaticInstBase : public RefCounted IsMicroOp, ///< Is a microop IsDelayedCommit, ///< This microop doesn't commit right away IsLastMicroOp, ///< This microop ends a microop sequence + IsFirstMicroOp, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop @@ -244,6 +245,7 @@ class StaticInstBase : public RefCounted bool isMicroOp() const { return flags[IsMicroOp]; } bool isDelayedCommit() const { return flags[IsDelayedCommit]; } bool isLastMicroOp() const { return flags[IsLastMicroOp]; } + bool isFirstMicroOp() const { return flags[IsFirstMicroOp]; } //This flag doesn't do anything yet bool isMicroBranch() const { return flags[IsMicroBranch]; } //@} -- cgit v1.2.3 From d6c92cdb3c9a8e13fddb58c89f13daac34390522 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:08:21 -0500 Subject: Fix legion lock code a bit so that if we jump out of a micro coded instruction (because of a fault on the first op) we don't lose sync with legion Only print TLB if there is a tlb difference --HG-- extra : convert_revision : f3baf667ca466d6b8efcaccd186ecec14498229d --- src/cpu/exetrace.cc | 54 ++++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 15 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 6e0bf6d33..87075c1ec 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -59,6 +59,7 @@ using namespace TheISA; #if THE_ISA == SPARC_ISA && FULL_SYSTEM static int diffcount = 0; +static bool wasMicro = false; #endif namespace Trace { @@ -124,6 +125,7 @@ inline void printLevelHeader(ostream & os, int level) void Trace::InstRecord::dump(ostream &outs) { + DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); if (flags[PRINT_REG_DELTA]) { #if THE_ISA == SPARC_ISA @@ -315,6 +317,24 @@ Trace::InstRecord::dump(ostream &outs) bool diffTlb = false; Addr m5Pc, lgnPc; + // We took a trap on a micro-op... + if (wasMicro && !staticInst->isMicroOp()) + { + // let's skip comparing this cycle + while (!compared) + if (shared_data->flags == OWN_M5) { + shared_data->flags = OWN_LEGION; + compared = true; + } + compared = false; + wasMicro = false; + } + + if (staticInst->isLastMicroOp()) + wasMicro = false; + else if (staticInst->isMicroOp()) + wasMicro = true; + if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { while (!compared) { @@ -587,24 +607,28 @@ Trace::InstRecord::dump(ostream &outs) << endl;*/ } } - printColumnLabels(outs); - char label[8]; - for (int x = 0; x < 64; x++) { - if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || - thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { - sprintf(label, "I-TLB:%02d", x); - printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]); + if (diffTlb) { + printColumnLabels(outs); + char label[8]; + for (int x = 0; x < 64; x++) { + if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || + thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { + sprintf(label, "I-TLB:%02d", x); + printRegPair(outs, label, thread->getITBPtr()->TteRead(x), + shared_data->itb[x]); + } } - } - for (int x = 0; x < 64; x++) { - if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || - thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { - sprintf(label, "D-TLB:%02d", x); - printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]); + for (int x = 0; x < 64; x++) { + if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || + thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { + sprintf(label, "D-TLB:%02d", x); + printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), + shared_data->dtb[x]); + } } + thread->getITBPtr()->dumpAll(); + thread->getDTBPtr()->dumpAll(); } - thread->getITBPtr()->dumpAll(); - thread->getDTBPtr()->dumpAll(); diffcount++; if (diffcount > 2) -- cgit v1.2.3 From 64528df38d7484591ae27bb2a2252fc1bccd4e9a Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 16 Jan 2007 19:12:33 -0500 Subject: In the case that we generate a fault (e.g. a tlb miss) on a microcoded instruction set curMacroStaticInst to null This way we'll jump immediately to the handler --HG-- extra : convert_revision : 36218d3a5c2342337e66e1229ea2219533efd41e --- src/cpu/simple/base.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4e5754bbb..ddccc5a9b 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -437,6 +437,7 @@ void BaseSimpleCPU::advancePC(Fault fault) { if (fault != NoFault) { + curMacroStaticInst = StaticInst::nullStaticInstPtr; fault->invoke(tc); } else { //If we're at the last micro op for this instruction -- cgit v1.2.3