From 1f6d5f8f849f50a3646f586b1274708537124ef3 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Sat, 20 Sep 2014 17:18:32 -0400 Subject: mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. --HG-- rename : src/mem/Bus.py => src/mem/XBar.py rename : src/mem/coherent_bus.cc => src/mem/coherent_xbar.cc rename : src/mem/coherent_bus.hh => src/mem/coherent_xbar.hh rename : src/mem/noncoherent_bus.cc => src/mem/noncoherent_xbar.cc rename : src/mem/noncoherent_bus.hh => src/mem/noncoherent_xbar.hh rename : src/mem/bus.cc => src/mem/xbar.cc rename : src/mem/bus.hh => src/mem/xbar.hh --- src/cpu/BaseCPU.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index b7f0b2089..8ba90209a 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -47,7 +47,7 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from Bus import CoherentBus +from XBar import CoherentXBar from InstTracer import InstTracer from ExeTracer import ExeTracer from MemObject import MemObject @@ -274,8 +274,8 @@ class BaseCPU(MemObject): self.itb_walker_cache = iwc self.dtb_walker_cache = dwc if buildEnv['TARGET_ISA'] in ['arm']: - self.itb_walker_cache_bus = CoherentBus() - self.dtb_walker_cache_bus = CoherentBus() + self.itb_walker_cache_bus = CoherentXBar() + self.dtb_walker_cache_bus = CoherentXBar() self.itb_walker_cache_bus.master = iwc.cpu_side self.dtb_walker_cache_bus.master = dwc.cpu_side self.itb.walker.port = self.itb_walker_cache_bus.slave @@ -308,7 +308,7 @@ class BaseCPU(MemObject): # Set a width of 32 bytes (256-bits), which is four times that # of the default bus. The clock of the CPU is inherited by # default. - self.toL2Bus = CoherentBus(width = 32) + self.toL2Bus = CoherentXBar(width = 32) self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side -- cgit v1.2.3