From 204e932607aa582cd7036b08e20521c2c6c49941 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 10 Jan 2019 17:28:05 +0000 Subject: cpu: O3 rename using the flatIndex instead of index This patch is replacing the RegId::index with RegId::flatIndex so that it provides a valid register number when used by a VecElem register. Change-Id: I5b000abb9457cd325c2a3021e772a75ea33d8a4c Signed-off-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/15600 Maintainer: Andreas Sandberg Reviewed-by: Andreas Sandberg --- src/cpu/o3/rename_map.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index d1876a965..1b831d940 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -76,14 +76,14 @@ SimpleRenameMap::rename(const RegId& arch_reg) PhysRegIdPtr renamed_reg; // Record the current physical register that is renamed to the // requested architected register. - PhysRegIdPtr prev_reg = map[arch_reg.index()]; + PhysRegIdPtr prev_reg = map[arch_reg.flatIndex()]; // If it's not referencing the zero register, then rename the // register. if (arch_reg != zeroReg) { renamed_reg = freeList->getReg(); - map[arch_reg.index()] = renamed_reg; + map[arch_reg.flatIndex()] = renamed_reg; } else { // Otherwise return the zero register so nothing bad happens. assert(prev_reg->isZeroReg()); @@ -92,8 +92,8 @@ SimpleRenameMap::rename(const RegId& arch_reg) DPRINTF(Rename, "Renamed reg %d to physical reg %d (%d) old mapping was" " %d (%d)\n", - arch_reg, renamed_reg->index(), renamed_reg->flatIndex(), - prev_reg->index(), prev_reg->flatIndex()); + arch_reg, renamed_reg->flatIndex(), renamed_reg->flatIndex(), + prev_reg->flatIndex(), prev_reg->flatIndex()); return RenameInfo(renamed_reg, prev_reg); } -- cgit v1.2.3