From 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 15 Oct 2012 08:12:35 -0400 Subject: Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. --- src/cpu/base.cc | 34 ++++++++++++---------- src/cpu/base.hh | 3 +- src/cpu/testers/directedtest/RubyDirectedTester.cc | 4 +-- src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 +-- src/cpu/testers/memtest/memtest.cc | 4 +-- src/cpu/testers/memtest/memtest.hh | 4 +-- src/cpu/testers/networktest/networktest.cc | 4 +-- src/cpu/testers/networktest/networktest.hh | 4 +-- src/cpu/testers/rubytest/RubyTester.cc | 6 ++-- src/cpu/testers/rubytest/RubyTester.hh | 4 +-- src/cpu/testers/traffic_gen/traffic_gen.cc | 4 +-- src/cpu/testers/traffic_gen/traffic_gen.hh | 4 +-- 12 files changed, 41 insertions(+), 38 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 1add92d1f..93c9f8629 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -296,8 +296,8 @@ BaseCPU::regStats() threadContexts[0]->regStats(name()); } -MasterPort & -BaseCPU::getMasterPort(const string &if_name, int idx) +BaseMasterPort & +BaseCPU::getMasterPort(const string &if_name, PortID idx) { // Get the right port based on name. This applies to all the // subclasses of the base CPU and relies on their implementation @@ -380,17 +380,17 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) ThreadContext::compare(oldTC, newTC); */ - MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); - MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); - MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); - MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); + BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); + BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); + BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); + BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); // Move over any table walker ports if they exist if (new_itb_port) { assert(!new_itb_port->isConnected()); assert(old_itb_port); assert(old_itb_port->isConnected()); - SlavePort &slavePort = old_itb_port->getSlavePort(); + BaseSlavePort &slavePort = old_itb_port->getSlavePort(); old_itb_port->unbind(); new_itb_port->bind(slavePort); } @@ -398,7 +398,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_dtb_port->isConnected()); assert(old_dtb_port); assert(old_dtb_port->isConnected()); - SlavePort &slavePort = old_dtb_port->getSlavePort(); + BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); old_dtb_port->unbind(); new_dtb_port->bind(slavePort); } @@ -408,13 +408,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); if (oldChecker && newChecker) { - MasterPort *old_checker_itb_port = + BaseMasterPort *old_checker_itb_port = oldChecker->getITBPtr()->getMasterPort(); - MasterPort *old_checker_dtb_port = + BaseMasterPort *old_checker_dtb_port = oldChecker->getDTBPtr()->getMasterPort(); - MasterPort *new_checker_itb_port = + BaseMasterPort *new_checker_itb_port = newChecker->getITBPtr()->getMasterPort(); - MasterPort *new_checker_dtb_port = + BaseMasterPort *new_checker_dtb_port = newChecker->getDTBPtr()->getMasterPort(); // Move over any table walker ports if they exist for checker @@ -422,7 +422,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_checker_itb_port->isConnected()); assert(old_checker_itb_port); assert(old_checker_itb_port->isConnected()); - SlavePort &slavePort = old_checker_itb_port->getSlavePort(); + BaseSlavePort &slavePort = + old_checker_itb_port->getSlavePort(); old_checker_itb_port->unbind(); new_checker_itb_port->bind(slavePort); } @@ -430,7 +431,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(!new_checker_dtb_port->isConnected()); assert(old_checker_dtb_port); assert(old_checker_dtb_port->isConnected()); - SlavePort &slavePort = old_checker_dtb_port->getSlavePort(); + BaseSlavePort &slavePort = + old_checker_dtb_port->getSlavePort(); old_checker_dtb_port->unbind(); new_checker_dtb_port->bind(slavePort); } @@ -455,13 +457,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) // we are switching to. assert(!getInstPort().isConnected()); assert(oldCPU->getInstPort().isConnected()); - SlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); + BaseSlavePort &inst_peer_port = oldCPU->getInstPort().getSlavePort(); oldCPU->getInstPort().unbind(); getInstPort().bind(inst_peer_port); assert(!getDataPort().isConnected()); assert(oldCPU->getDataPort().isConnected()); - SlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); + BaseSlavePort &data_peer_port = oldCPU->getDataPort().getSlavePort(); oldCPU->getDataPort().unbind(); getDataPort().bind(data_peer_port); } diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 0c1d19856..91cef24ed 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -171,7 +171,8 @@ class BaseCPU : public MemObject * * @return a reference to the port with the given name */ - MasterPort &getMasterPort(const std::string &if_name, int idx = -1); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); inline void workItemBegin() { numWorkItemsStarted++; } inline void workItemEnd() { numWorkItemsCompleted++; } diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.cc b/src/cpu/testers/directedtest/RubyDirectedTester.cc index 139798a72..70da23f03 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc @@ -74,8 +74,8 @@ RubyDirectedTester::init() generator->setDirectedTester(this); } -MasterPort & -RubyDirectedTester::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 325c60447..cb58fa63f 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -68,8 +68,8 @@ class RubyDirectedTester : public MemObject RubyDirectedTester(const Params *p); ~RubyDirectedTester(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); MasterPort* getCpuPort(int idx); diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index 7ea6ad84b..ea3e5fd9b 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -131,8 +131,8 @@ MemTest::MemTest(const Params *p) dmaOutstanding = false; } -MasterPort & -MemTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +MemTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "functional") return funcPort; diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 94617c876..cb5f8300f 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -59,8 +59,8 @@ class MemTest : public MemObject // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc index 3f61a87d3..8fff53aa7 100644 --- a/src/cpu/testers/networktest/networktest.cc +++ b/src/cpu/testers/networktest/networktest.cc @@ -97,8 +97,8 @@ NetworkTest::NetworkTest(const Params *p) name(), id); } -MasterPort & -NetworkTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +NetworkTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "test") return cachePort; diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh index 76119e678..253b48233 100644 --- a/src/cpu/testers/networktest/networktest.hh +++ b/src/cpu/testers/networktest/networktest.hh @@ -54,8 +54,8 @@ class NetworkTest : public MemObject // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index bdd6dacce..6ddab93e8 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -111,8 +111,8 @@ RubyTester::init() m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); } -MasterPort & -RubyTester::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyTester::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "cpuInstPort" && if_name != "cpuDataPort") { // pass it along to our super class @@ -134,7 +134,7 @@ RubyTester::getMasterPort(const std::string &if_name, int idx) // index // int read_idx = idx + m_num_inst_ports; - if (read_idx >= static_cast(readPorts.size())) { + if (read_idx >= static_cast(readPorts.size())) { panic("RubyTester::getMasterPort: unknown data port idx %d\n", idx); } diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index ad4b506ac..2fed84e2d 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -89,8 +89,8 @@ class RubyTester : public MemObject RubyTester(const Params *p); ~RubyTester(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); bool isInstReadableCpuPort(int idx); diff --git a/src/cpu/testers/traffic_gen/traffic_gen.cc b/src/cpu/testers/traffic_gen/traffic_gen.cc index 054900b20..af7ff89f4 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.cc +++ b/src/cpu/testers/traffic_gen/traffic_gen.cc @@ -66,8 +66,8 @@ TrafficGenParams::create() return new TrafficGen(this); } -MasterPort& -TrafficGen::getMasterPort(const string& if_name, int idx) +BaseMasterPort& +TrafficGen::getMasterPort(const string& if_name, PortID idx) { if (if_name == "port") { return port; diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh index 19182fa15..5f59be82c 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.hh +++ b/src/cpu/testers/traffic_gen/traffic_gen.hh @@ -597,8 +597,8 @@ class TrafficGen : public MemObject ~TrafficGen() {} - virtual MasterPort& getMasterPort(const std::string &if_name, - int idx = InvalidPortID); + virtual BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); void init(); -- cgit v1.2.3