From 2b7d4bd73db443b4ca302213689a673266e856e0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 9 Oct 2019 21:04:22 -0700 Subject: cpu,sim: Get rid of a bunch of conditional compilation for PCEvents. These can now be built without referring to anything in ThreadContext and so can be built even with the NULL ISA. This means the pcEventQueue can be unconditionally built into the System class. Even though the pcEventQueue is going away, this still makes it possible for System to be a PCEventScope unconditionally. Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104 Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- src/cpu/SConscript | 3 ++- src/cpu/pc_event.cc | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/SConscript b/src/cpu/SConscript index a8585a797..bd6639061 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -72,6 +72,8 @@ CompoundFlag('ExecNoTicks', [ 'ExecEnable', 'ExecOpClass', 'ExecThread', 'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting', 'ExecUser', 'ExecKernel' ]) +Source('pc_event.cc') + if env['TARGET_ISA'] == 'null': SimObject('IntrControl.py') Source('intr_control_noisa.cc') @@ -99,7 +101,6 @@ Source('func_unit.cc') Source('inteltrace.cc') Source('intr_control.cc') Source('nativetrace.cc') -Source('pc_event.cc') Source('profile.cc') Source('quiesce_event.cc') Source('reg_class.cc') diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index b4017de7a..0bb8a4175 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -37,8 +37,6 @@ #include "base/debug.hh" #include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" #include "debug/PCEvent.hh" #include "sim/core.hh" #include "sim/system.hh" -- cgit v1.2.3