From 592f35ac0ff8d525fad2dc606b53b4cd8b84fd69 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 2 Feb 2007 18:04:42 -0500 Subject: fix mostly floating point related src/arch/sparc/floatregfile.cc: fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them src/arch/sparc/isa/decoder.isa: fix some fp implementations src/arch/sparc/isa/formats/basic.isa: add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op src/arch/sparc/isa/includes.isa: include the appropriate header files for the rounding code src/arch/sparc/miscregfile.cc: print fsr out when it's read/written and the Sparc traceflgas in on src/cpu/exetrace.cc: fix printing of float registers --HG-- extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992 --- src/cpu/exetrace.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index e34ae3731..672b06eaf 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -450,16 +450,13 @@ Trace::InstRecord::dump(ostream &outs) diffTlb = true; } - if ((diffPC || diffCC || diffInst || diffIntRegs || + if (diffPC || diffCC || diffInst || diffIntRegs || diffFpRegs || diffTpc || diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffFsr || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) - && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) - && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) - && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) - ) { + { outs << "Differences found between M5 and Legion:"; if (diffPC) @@ -639,7 +636,7 @@ Trace::InstRecord::dump(ostream &outs) char label[8]; sprintf(label, "%%f%d", x); printRegPair(outs, label, - thread->readFloatRegBits(x,FloatRegFile::DoubleWidth), + thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), shared_data->fpregs[x]); } } -- cgit v1.2.3 From ebb6972dd3a6b9343c79fd022756523a2992a264 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 6 Feb 2007 15:52:33 -0500 Subject: more fp fixes fix unaligned accesses in mmaped disk device src/arch/sparc/isa/decoder.isa: get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code src/arch/sparc/isa/formats/basic.isa: move the cexec into the aexec field src/cpu/exetrace.cc: copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer src/dev/sparc/mm_disk.cc: src/dev/sparc/mm_disk.hh: fix unaligned accesses in the memory mapped disk device --HG-- extra : convert_revision : aaa33096b08cf0563fe291d984a87493a117e528 --- src/cpu/exetrace.cc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 672b06eaf..5108d7338 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -411,8 +411,14 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->y != thread->readIntReg(NumIntArchRegs + 1)) diffY = true; - if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) + if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) { diffFsr = true; + if (mbits(shared_data->fsr, 63,10) == + mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) { + thread->setMiscReg(MISCREG_FSR, shared_data->fsr); + diffFsr = false; + } + } //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR)) if(shared_data->ccr != thread->readIntReg(NumIntArchRegs + 2)) @@ -664,7 +670,7 @@ Trace::InstRecord::dump(ostream &outs) } diffcount++; - if (diffcount > 2) + if (diffcount > 3) fatal("Differences found between Legion and M5\n"); } else diffcount = 0; -- cgit v1.2.3