From 7a39457d7ff5fd80484061a4ff7006921899b229 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:17 -0800 Subject: X86: Make the micropc available through the thread context objects. This is necssary for fault handlers that branch to non-zero micro PCs. --HG-- extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264 --- src/cpu/o3/thread_context.hh | 10 ++++++++++ src/cpu/o3/thread_context_impl.hh | 30 +++++++++++++++++++++++++++++- src/cpu/thread_context.hh | 16 ++++++++++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 31e08db4c..55b385d11 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -203,6 +203,16 @@ class O3ThreadContext : public ThreadContext /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); + virtual uint64_t readMicroPC() + { return cpu->readMicroPC(thread->readTid()); } + + virtual void setMicroPC(uint64_t val); + + virtual uint64_t readNextMicroPC() + { return cpu->readNextMicroPC(thread->readTid()); } + + virtual void setNextMicroPC(uint64_t val); + /** Reads a miscellaneous register. */ virtual MiscReg readMiscRegNoEffect(int misc_reg) { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index efbbc2329..55584629e 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -289,9 +289,13 @@ O3ThreadContext::copyArchRegs(ThreadContext *tc) // Copy the misc regs. TheISA::copyMiscRegs(tc, this); - // Then finally set the PC and the next PC. + // Then finally set the PC, the next PC, the nextNPC, the micropc, and the + // next micropc. cpu->setPC(tc->readPC(), tid); cpu->setNextPC(tc->readNextPC(), tid); + cpu->setNextNPC(tc->readNextNPC(), tid); + cpu->setMicroPC(tc->readMicroPC(), tid); + cpu->setNextMicroPC(tc->readNextMicroPC(), tid); #if !FULL_SYSTEM this->thread->funcExeInst = tc->readFuncExeInst(); #endif @@ -448,6 +452,30 @@ O3ThreadContext::setNextPC(uint64_t val) } } +template +void +O3ThreadContext::setMicroPC(uint64_t val) +{ + cpu->setMicroPC(val, thread->readTid()); + + // Squash if we're not already in a state update mode. + if (!thread->trapPending && !thread->inSyscall) { + cpu->squashFromTC(thread->readTid()); + } +} + +template +void +O3ThreadContext::setNextMicroPC(uint64_t val) +{ + cpu->setNextMicroPC(val, thread->readTid()); + + // Squash if we're not already in a state update mode. + if (!thread->trapPending && !thread->inSyscall) { + cpu->squashFromTC(thread->readTid()); + } +} + template void O3ThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 31fdb42c2..0d09492ee 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -226,6 +226,14 @@ class ThreadContext virtual void setNextNPC(uint64_t val) = 0; + virtual uint64_t readMicroPC() = 0; + + virtual void setMicroPC(uint64_t val) = 0; + + virtual uint64_t readNextMicroPC() = 0; + + virtual void setNextMicroPC(uint64_t val) = 0; + virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; virtual MiscReg readMiscReg(int misc_reg) = 0; @@ -419,6 +427,14 @@ class ProxyThreadContext : public ThreadContext void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } + uint64_t readMicroPC() { return actualTC->readMicroPC(); } + + void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } + + uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } + + void setNextMicroPC(uint64_t val) { actualTC->setMicroPC(val); } + MiscReg readMiscRegNoEffect(int misc_reg) { return actualTC->readMiscRegNoEffect(misc_reg); } -- cgit v1.2.3 From f17f3d20be08d25f176138691a29897df54e5cc0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:24 -0800 Subject: X86: Implement a page table walker. --HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec --- src/cpu/BaseCPU.py | 9 ++++++++- src/cpu/o3/O3CPU.py | 2 +- src/cpu/simple/AtomicSimpleCPU.py | 3 ++- src/cpu/simple/TimingSimpleCPU.py | 2 +- 4 files changed, 12 insertions(+), 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 9b2b99c58..1af30a532 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -100,18 +100,25 @@ class BaseCPU(SimObject): _mem_ports = [] + if build_env['TARGET_ISA'] == 'x86': + itb.walker_port = Port("ITB page table walker port") + dtb.walker_port = Port("ITB page table walker port") + _mem_ports = ["itb.walker_port", "dtb.walker_port"] + def connectMemPorts(self, bus): for p in self._mem_ports: if p != 'physmem_port': exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) + assert(len(self._mem_ports) < 6) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] + if build_env['TARGET_ISA'] == 'x86': + self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 27ca8ce1e..f0284b2cf 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -58,7 +58,7 @@ class DerivO3CPU(BaseCPU): cachePorts = Param.Unsigned(200, "Cache Ports") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index bfd1825c2..28c2aa9c9 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -41,4 +41,5 @@ class AtomicSimpleCPU(BaseCPU): icache_port = Port("Instruction Port") dcache_port = Port("Data Port") physmem_port = Port("Physical Memory Port") - _mem_ports = ['icache_port', 'dcache_port', 'physmem_port'] + _mem_ports = BaseCPU._mem_ports + \ + ['icache_port', 'dcache_port', 'physmem_port'] diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 2fcde175c..7e777e813 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU): profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") - _mem_ports = ['icache_port', 'dcache_port'] + _mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port'] -- cgit v1.2.3 From fce45baf178b43c2ea1476967fba3766e9b2ea9d Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 14:38:31 -0800 Subject: X86: Work on the page table walker, TLB, and related faults. --HG-- extra : convert_revision : 9edde958b7e571c07072785f18f9109f73b8059f --- src/cpu/BaseCPU.py | 4 ++-- src/cpu/simple/base.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 1af30a532..cb5793e57 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -100,7 +100,7 @@ class BaseCPU(SimObject): _mem_ports = [] - if build_env['TARGET_ISA'] == 'x86': + if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: itb.walker_port = Port("ITB page table walker port") dtb.walker_port = Port("ITB page table walker port") _mem_ports = ["itb.walker_port", "dtb.walker_port"] @@ -117,7 +117,7 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] - if build_env['TARGET_ISA'] == 'x86': + if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 1611a7275..98e29d8d1 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault) if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; predecoder.reset(); - fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); + fault->invoke(tc); } else { //If we're at the last micro op for this instruction if (curStaticInst && curStaticInst->isLastMicroop()) { -- cgit v1.2.3 From 1048b548fabfb7af2113f226f2151d3eb0e63289 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 12 Nov 2007 18:06:57 -0800 Subject: X86: Separate out the page table walker into it's own cc and hh. --HG-- extra : convert_revision : cbc3af01ca3dc911a59224a574007c5c0bcf6042 --- src/cpu/BaseCPU.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index cb5793e57..9fc1db9f1 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -101,9 +101,7 @@ class BaseCPU(SimObject): _mem_ports = [] if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - itb.walker_port = Port("ITB page table walker port") - dtb.walker_port = Port("ITB page table walker port") - _mem_ports = ["itb.walker_port", "dtb.walker_port"] + _mem_ports = ["itb.walker.port", "dtb.walker.port"] def connectMemPorts(self, bus): for p in self._mem_ports: -- cgit v1.2.3