From 4b68652c87f61fe0a2fd4040b79130de0846df85 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Mon, 2 Jul 2007 13:57:45 -0700 Subject: Couple more minor bug fixes for FS timing mode. src/cpu/simple/timing.cc: Fix another SC problem. src/mem/cache/cache_impl.hh: Forgot to call makeTimingResponse() on uncached timing responses. --HG-- extra : convert_revision : 5a5a58ca2053e4e8de2133205bfd37de15eb4209 --- src/cpu/simple/timing.cc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 492a669b8..0c03815b5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -356,8 +356,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access - assert(dcache_pkt == NULL); - if (req->isLocked()) { cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req); @@ -369,11 +367,14 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } - if (do_access) { - dcache_pkt = new Packet(req, cmd, Packet::Broadcast); - dcache_pkt->allocate(); - dcache_pkt->set(data); + // Note: need to allocate dcache_pkt even if do_access is + // false, as it's used unconditionally to call completeAcc(). + assert(dcache_pkt == NULL); + dcache_pkt = new Packet(req, cmd, Packet::Broadcast); + dcache_pkt->allocate(); + dcache_pkt->set(data); + if (do_access) { if (!dcachePort.sendTiming(dcache_pkt)) { _status = DcacheRetry; } else { -- cgit v1.2.3