From 4e8d2d1593475008b926829e6944a59963166079 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 2 Mar 2007 22:34:51 -0500 Subject: make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42 --- src/cpu/simple/atomic.cc | 4 ++++ src/cpu/simple/timing.cc | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src/cpu') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 3001241fe..df7e780e6 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -319,6 +319,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) #ifndef DOXYGEN_SHOULD_SKIP_THIS +template +Fault +AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); + template Fault AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ff3606a74..7f857c68d 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -315,6 +315,10 @@ template Fault TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); +template +Fault +TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags); + template Fault TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); -- cgit v1.2.3