From 024b33a1ef6f83be634f7afe644777f070ccd692 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 11 Oct 2006 18:44:48 -0400 Subject: some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong. src/cpu/simple/atomic.cc: memory mode assertion change so that it only goes off if it's supposed to. src/cpu/simple/timing.cc: some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to. --HG-- extra : convert_revision : 007d8610f097e08f01367b905ada49f93cf37ca3 --- src/cpu/simple/atomic.cc | 2 +- src/cpu/simple/timing.cc | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 11 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 490be20ae..fe421ae6c 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -182,9 +182,9 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion) void AtomicSimpleCPU::resume() { - assert(system->getMemoryMode() == System::Atomic); changeState(SimObject::Running); if (thread->status() == ThreadContext::Active) { + assert(system->getMemoryMode() == System::Atomic); if (!tickEvent.scheduled()) tickEvent.schedule(curTick); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 48362c42a..88aa882e3 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -146,6 +146,8 @@ void TimingSimpleCPU::resume() { if (_status != SwitchedOut && _status != Idle) { + assert(system->getMemoryMode() == System::Timing); + // Delete the old event if it existed. if (fetchEvent) { if (fetchEvent->scheduled()) @@ -159,7 +161,6 @@ TimingSimpleCPU::resume() fetchEvent->schedule(curTick); } - assert(system->getMemoryMode() == System::Timing); changeState(SimObject::Running); } @@ -190,6 +191,10 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU) break; } } + + if (_status != Running) { + _status = Idle; + } } @@ -533,15 +538,6 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt) assert(_status == DcacheWaitResponse); _status = Running; - if (getState() == SimObject::Draining) { - completeDrain(); - - delete pkt->req; - delete pkt; - - return; - } - Fault fault = curStaticInst->completeAcc(pkt, this, traceData); if (pkt->isRead() && pkt->req->isLocked()) { @@ -551,6 +547,13 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt) delete pkt->req; delete pkt; + if (getState() == SimObject::Draining) { + advancePC(fault); + completeDrain(); + + return; + } + postExecute(); advanceInst(fault); } -- cgit v1.2.3 From dd18ffe51d7dbef59804e7af3384fe0cc28447a5 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 12 Oct 2006 13:43:12 -0400 Subject: Fix a memory leak in the memtester --HG-- extra : convert_revision : 93062b0f1a3ba7a5210e2f27099f20ae8f66522b --- src/cpu/memtest/memtest.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index f42f0f8e2..c44f28f9b 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -360,7 +360,11 @@ MemTest::tick() //For now we only allow one outstanding request per addreess per tester //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. - if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return; + if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { + delete result; + delete req; + return; + } else outstandingAddrs.insert(paddr); // ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin @@ -395,7 +399,12 @@ MemTest::tick() //For now we only allow one outstanding request per addreess per tester //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. - if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) return; + if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { + delete result; + delete req; + return; + } + else outstandingAddrs.insert(paddr); /* -- cgit v1.2.3 From 6ffdc7b4d7be6d27be3a1ae83262787565063b36 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 12 Oct 2006 13:45:28 -0400 Subject: Another memleak in the memtester (need [] with the delete) src/cpu/memtest/memtest.cc: Another memleak in the memtester --HG-- extra : convert_revision : f7ab079e90d578fb6b9d1ff238d049fcce55b01b --- src/cpu/memtest/memtest.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index c44f28f9b..024cd7e41 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -400,7 +400,7 @@ MemTest::tick() //This means we assume CPU does write forwarding to reads that alias something //in the cpu store buffer. if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) { - delete result; + delete [] result; delete req; return; } -- cgit v1.2.3 From a50e83c1340de76f61ca8cf16fccb0ba09393580 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 13 Oct 2006 17:35:23 -0400 Subject: Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug). src/cpu/o3/fetch_impl.hh: Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash). --HG-- extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018 --- src/cpu/o3/fetch_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 32210f1cd..07d4ebb42 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1285,8 +1285,8 @@ template void DefaultFetch::recvRetry() { - assert(cacheBlocked); if (retryPkt != NULL) { + assert(cacheBlocked); assert(retryTid != -1); assert(fetchStatus[retryTid] == IcacheWaitRetry); -- cgit v1.2.3