From b2eecd643c1706d0d070568d5370aafa3910c104 Mon Sep 17 00:00:00 2001
From: Ali Saidi <saidi@eecs.umich.edu>
Date: Wed, 29 Nov 2006 17:11:10 -0500
Subject: Add support for mmapped iprs to atomic cpu

src/arch/SConscript:
    add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
    make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
    miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
    implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
    add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
    allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits

--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
---
 src/cpu/simple/atomic.cc | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index cd335e36d..b7699c405 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
 #include "arch/utility.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/simple/atomic.hh"
@@ -285,7 +286,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     if (fault == NoFault) {
         pkt->reinitFromRequest();
 
-        dcache_latency = dcachePort.sendAtomic(pkt);
+        if (req->isMmapedIpr())
+            dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
+        else
+            dcache_latency = dcachePort.sendAtomic(pkt);
         dcache_access = true;
 
         assert(pkt->result == Packet::Success);
@@ -372,11 +376,15 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         }
 
         if (do_access) {
-            data = htog(data);
             pkt->reinitFromRequest();
             pkt->dataStatic(&data);
 
-            dcache_latency = dcachePort.sendAtomic(pkt);
+            if (req->isMmapedIpr()) {
+                dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
+            } else {
+                data = htog(data);
+                dcache_latency = dcachePort.sendAtomic(pkt);
+            }
             dcache_access = true;
 
             assert(pkt->result == Packet::Success);
-- 
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