From 5592798865ece858bab2b444bc782d19121e2566 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 6 Feb 2016 17:21:19 -0800 Subject: style: fix missing spaces in control statements Result of running 'hg m5style --skip-all --fix-control -a'. --- src/cpu/base.cc | 8 ++++---- src/cpu/kvm/perfevent.cc | 2 +- src/cpu/kvm/x86_cpu.cc | 10 +++++----- src/cpu/minor/decode.cc | 2 +- src/cpu/nativetrace.cc | 2 +- src/cpu/nativetrace.hh | 2 +- src/cpu/o3/inst_queue_impl.hh | 2 +- src/cpu/o3/rename_impl.hh | 2 +- src/cpu/pred/bpred_unit.cc | 2 +- src/cpu/simple/atomic.cc | 12 ++++++------ src/cpu/simple/base.cc | 2 +- src/cpu/simple/timing.cc | 4 ++-- 12 files changed, 25 insertions(+), 25 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 9ba7e08a7..77677759f 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -98,7 +98,7 @@ CPUProgressEvent::process() if (_repeatEvent) cpu->schedule(this, curTick() + _interval); - if(cpu->switchedOut()) { + if (cpu->switchedOut()) { return; } @@ -288,7 +288,7 @@ BaseCPU::mwait(ThreadID tid, PacketPtr pkt) assert(tid < numThreads); AddressMonitor &monitor = addressMonitor[tid]; - if(monitor.gotWakeup == false) { + if (monitor.gotWakeup == false) { int block_size = cacheLineSize(); uint64_t mask = ~((uint64_t)(block_size - 1)); @@ -701,8 +701,8 @@ AddressMonitor::AddressMonitor() { bool AddressMonitor::doMonitor(PacketPtr pkt) { assert(pkt->req->hasPaddr()); - if(armed && waiting) { - if(pAddr == pkt->getAddr()) { + if (armed && waiting) { + if (pAddr == pkt->getAddr()) { DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n", pkt->getAddr()); waiting = false; diff --git a/src/cpu/kvm/perfevent.cc b/src/cpu/kvm/perfevent.cc index cd8b970e9..acc2af04b 100644 --- a/src/cpu/kvm/perfevent.cc +++ b/src/cpu/kvm/perfevent.cc @@ -242,5 +242,5 @@ PerfKvmCounter::read(void *buf, size_t size) const _buf += ret; break; } - } while(_size); + } while (_size); } diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc index 5312ca55a..f3e5edaed 100644 --- a/src/cpu/kvm/x86_cpu.cc +++ b/src/cpu/kvm/x86_cpu.cc @@ -118,7 +118,7 @@ static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave"); APPLY_IREG(r13, INTREG_R13); \ APPLY_IREG(r14, INTREG_R14); \ APPLY_IREG(r15, INTREG_R15); \ - } while(0) + } while (0) #define FOREACH_SREG() \ do { \ @@ -129,7 +129,7 @@ static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave"); APPLY_SREG(cr8, MISCREG_CR8); \ APPLY_SREG(efer, MISCREG_EFER); \ APPLY_SREG(apic_base, MISCREG_APIC_BASE); \ - } while(0) + } while (0) #define FOREACH_DREG() \ do { \ @@ -139,7 +139,7 @@ static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave"); APPLY_DREG(db[3], MISCREG_DR3); \ APPLY_DREG(dr6, MISCREG_DR6); \ APPLY_DREG(dr7, MISCREG_DR7); \ - } while(0) + } while (0) #define FOREACH_SEGMENT() \ do { \ @@ -151,13 +151,13 @@ static_assert(sizeof(FXSave) == 512, "Unexpected size of FXSave"); APPLY_SEGMENT(ss, MISCREG_SS - MISCREG_SEG_SEL_BASE); \ APPLY_SEGMENT(tr, MISCREG_TR - MISCREG_SEG_SEL_BASE); \ APPLY_SEGMENT(ldt, MISCREG_TSL - MISCREG_SEG_SEL_BASE); \ - } while(0) + } while (0) #define FOREACH_DTABLE() \ do { \ APPLY_DTABLE(gdt, MISCREG_TSG - MISCREG_SEG_SEL_BASE); \ APPLY_DTABLE(idt, MISCREG_IDTR - MISCREG_SEG_SEL_BASE); \ - } while(0) + } while (0) template static STRUCT *newVarStruct(size_t entries) diff --git a/src/cpu/minor/decode.cc b/src/cpu/minor/decode.cc index 533ebd7d3..94eee2be3 100644 --- a/src/cpu/minor/decode.cc +++ b/src/cpu/minor/decode.cc @@ -226,7 +226,7 @@ Decode::evaluate() execSeqNum++; /* Correctly size the output before writing */ - if(output_index == 0) insts_out.resize(outputWidth); + if (output_index == 0) insts_out.resize(outputWidth); /* Push into output */ insts_out.insts[output_index] = output_inst; output_index++; diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc index 1f5132288..6d1655ba7 100644 --- a/src/cpu/nativetrace.cc +++ b/src/cpu/nativetrace.cc @@ -45,7 +45,7 @@ NativeTrace::NativeTrace(const Params *p) fatal("All listeners are disabled!"); int port = 8000; - while(!native_listener.listen(port, true)) + while (!native_listener.listen(port, true)) { DPRINTF(GDBMisc, "Can't bind port %d\n", port); port++; diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh index d91dbd6ec..528e3bf65 100644 --- a/src/cpu/nativetrace.hh +++ b/src/cpu/nativetrace.hh @@ -90,7 +90,7 @@ class NativeTrace : public ExeTracer bool checkReg(const char * regName, T &val, T &realVal) { - if(val != realVal) + if (val != realVal) { DPRINTFN("Register %s should be %#x but is %#x.\n", regName, realVal, val); diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index 7d359b992..516d526b1 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -498,7 +498,7 @@ InstructionQueue::resetEntries() if (iqPolicy == Partitioned) { maxEntries[tid] = numEntries / active_threads; - } else if(iqPolicy == Threshold && active_threads == 1) { + } else if (iqPolicy == Threshold && active_threads == 1) { maxEntries[tid] = numEntries; } } diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index b19b3414c..b6ab4cc3a 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -766,7 +766,7 @@ DefaultRename::skidInsert(ThreadID tid) { typename InstQueue::iterator it; warn("Skidbuffer contents:\n"); - for(it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) + for (it = skidBuffer[tid].begin(); it != skidBuffer[tid].end(); it++) { warn("[tid:%u]: %s [sn:%i].\n", tid, (*it)->staticInst->disassemble(inst->instAddr()), diff --git a/src/cpu/pred/bpred_unit.cc b/src/cpu/pred/bpred_unit.cc index a5e1ffd59..8bb84f836 100644 --- a/src/cpu/pred/bpred_unit.cc +++ b/src/cpu/pred/bpred_unit.cc @@ -415,7 +415,7 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid) RAS[tid].restore(pred_hist.front().RASIndex, pred_hist.front().RASTarget); - } else if(pred_hist.front().wasCall && pred_hist.front().pushedRAS) { + } else if (pred_hist.front().wasCall && pred_hist.front().pushedRAS) { // Was a call but predicated false. Pop RAS here DPRINTF(Branch, "[tid: %i] Squashing" " Call [sn:%i] PC: %s Popping RAS\n", tid, diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 4afd019d0..1eb219483 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -139,7 +139,7 @@ AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) for (ThreadID tid = 0; tid < numThreads; tid++) { if (tid != sender) { - if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { + if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { wakeup(tid); } @@ -312,7 +312,7 @@ AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) // X86 ISA: Snooping an invalidation for monitor/mwait AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner); for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { - if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { + if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { cpu->wakeup(tid); } } @@ -450,13 +450,13 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, //across a cache line boundary. Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); - if(secondAddr > addr) + if (secondAddr > addr) size = secondAddr - addr; dcache_latency = 0; req->taskId(taskId()); - while(1) { + while (1) { req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); // translate to physical address @@ -600,7 +600,7 @@ AtomicSimpleCPU::tick() // like the I cache. It should be flushed, and when that works // this code should be uncommented. //Fetch more instruction memory if necessary - //if(decoder.needMoreBytes()) + //if (decoder.needMoreBytes()) //{ icache_access = true; Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); @@ -657,7 +657,7 @@ AtomicSimpleCPU::tick() } } - if(fault != NoFault || !t_info.stayAtPC) + if (fault != NoFault || !t_info.stayAtPC) advancePC(fault); } diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 4d5ddebb2..bd6861102 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -497,7 +497,7 @@ BaseSimpleCPU::preExecute() //Predecode, ie bundle up an ExtMachInst //If more fetch data is needed, pass it in. Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset; - //if(decoder->needMoreBytes()) + //if (decoder->needMoreBytes()) decoder->moreBytes(pcState, fetchPC, inst); //else // decoder->process(); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 97a280b17..da6427306 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -551,7 +551,7 @@ TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender) { for (ThreadID tid = 0; tid < numThreads; tid++) { if (tid != sender) { - if(getCpuAddrMonitor(tid)->doMonitor(pkt)) { + if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { wakeup(tid); } TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt, @@ -885,7 +885,7 @@ void TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt) { for (ThreadID tid = 0; tid < cpu->numThreads; tid++) { - if(cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { + if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) { cpu->wakeup(tid); } } -- cgit v1.2.3