From 592f35ac0ff8d525fad2dc606b53b4cd8b84fd69 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Fri, 2 Feb 2007 18:04:42 -0500 Subject: fix mostly floating point related src/arch/sparc/floatregfile.cc: fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them src/arch/sparc/isa/decoder.isa: fix some fp implementations src/arch/sparc/isa/formats/basic.isa: add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op src/arch/sparc/isa/includes.isa: include the appropriate header files for the rounding code src/arch/sparc/miscregfile.cc: print fsr out when it's read/written and the Sparc traceflgas in on src/cpu/exetrace.cc: fix printing of float registers --HG-- extra : convert_revision : 49faab27f2e786a8455f9ca0f3f0132380c9d992 --- src/cpu/exetrace.cc | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index e34ae3731..672b06eaf 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -450,16 +450,13 @@ Trace::InstRecord::dump(ostream &outs) diffTlb = true; } - if ((diffPC || diffCC || diffInst || diffIntRegs || + if (diffPC || diffCC || diffInst || diffIntRegs || diffFpRegs || diffTpc || diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffFsr || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || diffOtherwin || diffCleanwin || diffTlb) - && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) - && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) - && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) - ) { + { outs << "Differences found between M5 and Legion:"; if (diffPC) @@ -639,7 +636,7 @@ Trace::InstRecord::dump(ostream &outs) char label[8]; sprintf(label, "%%f%d", x); printRegPair(outs, label, - thread->readFloatRegBits(x,FloatRegFile::DoubleWidth), + thread->readFloatRegBits(x*2,FloatRegFile::DoubleWidth), shared_data->fpregs[x]); } } -- cgit v1.2.3