From 61c14da751ae80e8c19e0b63ddd629c4152f1c72 Mon Sep 17 00:00:00 2001 From: Chander Sudanthi Date: Thu, 1 Dec 2011 00:15:22 -0800 Subject: O3: Remove hardcoded tgts_per_mshr in O3CPU.py. There are two lines in O3CPU.py that set the dcache and icache tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr. This patch removes these hardcoded lines from O3CPU.py and sets the default L1 cache mshr targets to 20. --HG-- extra : rebase_source : 6f92d950e90496a3102967442814e97dc84db08b --- src/cpu/o3/O3CPU.py | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index 47b18a3ec..2a5b6782f 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -146,7 +146,3 @@ class DerivO3CPU(BaseCPU): smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") - def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): - BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc) - self.icache.tgts_per_mshr = 20 - self.dcache.tgts_per_mshr = 20 -- cgit v1.2.3