From 672d6a4b98165952e0afa0057f851f150bc657ec Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 20 Dec 2010 16:24:40 -0500 Subject: Style: Replace some tabs with spaces. --- src/cpu/inorder/SConscript | 106 ++++++++++++++++---------------- src/cpu/inorder/first_stage.hh | 2 +- src/cpu/inorder/inorder_dyn_inst.hh | 30 ++++----- src/cpu/inorder/resource.hh | 2 +- src/cpu/inorder/resources/cache_unit.hh | 2 +- 5 files changed, 71 insertions(+), 71 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript index 90cb285f5..37c235759 100644 --- a/src/cpu/inorder/SConscript +++ b/src/cpu/inorder/SConscript @@ -31,60 +31,60 @@ Import('*') if 'InOrderCPU' in env['CPU_MODELS']: - SimObject('InOrderCPU.py') - SimObject('InOrderTrace.py') + SimObject('InOrderCPU.py') + SimObject('InOrderTrace.py') - TraceFlag('ResReqCount') - TraceFlag('InOrderStage') - TraceFlag('InOrderStall') - TraceFlag('InOrderCPU') - TraceFlag('RegDepMap') - TraceFlag('InOrderDynInst') - TraceFlag('Resource') - TraceFlag('InOrderAGEN') - TraceFlag('InOrderFetchSeq') - TraceFlag('InOrderTLB') - TraceFlag('InOrderCachePort') - TraceFlag('InOrderBPred') - TraceFlag('InOrderDecode') - TraceFlag('InOrderExecute') - TraceFlag('InOrderInstBuffer') - TraceFlag('InOrderUseDef') - TraceFlag('InOrderMDU') - TraceFlag('InOrderGraduation') - TraceFlag('ThreadModel') - TraceFlag('RefCount') - TraceFlag('AddrDep') - + TraceFlag('ResReqCount') + TraceFlag('InOrderStage') + TraceFlag('InOrderStall') + TraceFlag('InOrderCPU') + TraceFlag('RegDepMap') + TraceFlag('InOrderDynInst') + TraceFlag('Resource') + TraceFlag('InOrderAGEN') + TraceFlag('InOrderFetchSeq') + TraceFlag('InOrderTLB') + TraceFlag('InOrderCachePort') + TraceFlag('InOrderBPred') + TraceFlag('InOrderDecode') + TraceFlag('InOrderExecute') + TraceFlag('InOrderInstBuffer') + TraceFlag('InOrderUseDef') + TraceFlag('InOrderMDU') + TraceFlag('InOrderGraduation') + TraceFlag('ThreadModel') + TraceFlag('RefCount') + TraceFlag('AddrDep') - CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', - 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', - 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef', - 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource', - 'ThreadModel', 'AddrDep']) - Source('pipeline_traits.cc') - Source('inorder_dyn_inst.cc') - Source('inorder_cpu_builder.cc') - Source('inorder_trace.cc') - Source('pipeline_stage.cc') - Source('first_stage.cc') - Source('resource.cc') - Source('resources/agen_unit.cc') - Source('resources/execution_unit.cc') - Source('resources/bpred_unit.cc') - Source('resources/branch_predictor.cc') - Source('resources/cache_unit.cc') - Source('resources/use_def.cc') - Source('resources/decode_unit.cc') - Source('resources/inst_buffer.cc') - Source('resources/graduation_unit.cc') - Source('resources/fetch_seq_unit.cc') - Source('resources/mult_div_unit.cc') - Source('resource_pool.cc') - Source('resource_sked.cc') - Source('reg_dep_map.cc') - Source('thread_state.cc') - Source('thread_context.cc') - Source('cpu.cc') + CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', + 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', + 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef', + 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource', + 'ThreadModel', 'AddrDep']) + + Source('pipeline_traits.cc') + Source('inorder_dyn_inst.cc') + Source('inorder_cpu_builder.cc') + Source('inorder_trace.cc') + Source('pipeline_stage.cc') + Source('first_stage.cc') + Source('resource.cc') + Source('resources/agen_unit.cc') + Source('resources/execution_unit.cc') + Source('resources/bpred_unit.cc') + Source('resources/branch_predictor.cc') + Source('resources/cache_unit.cc') + Source('resources/use_def.cc') + Source('resources/decode_unit.cc') + Source('resources/inst_buffer.cc') + Source('resources/graduation_unit.cc') + Source('resources/fetch_seq_unit.cc') + Source('resources/mult_div_unit.cc') + Source('resource_pool.cc') + Source('resource_sked.cc') + Source('reg_dep_map.cc') + Source('thread_state.cc') + Source('thread_context.cc') + Source('cpu.cc') diff --git a/src/cpu/inorder/first_stage.hh b/src/cpu/inorder/first_stage.hh index 383b799f3..f479dd812 100644 --- a/src/cpu/inorder/first_stage.hh +++ b/src/cpu/inorder/first_stage.hh @@ -64,7 +64,7 @@ class FirstStage : public PipelineStage { void squashDueToMemStall(InstSeqNum seq_num, ThreadID tid); /** There are no insts. coming from previous stages, so there is - * no need to sort insts here + * no need to sort insts here */ void sortInsts() {} diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index a67fe46c2..1c0ee4384 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -101,8 +101,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted typedef std::list::iterator ListIt; enum { - MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs - MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs + MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs + MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs }; public: @@ -373,24 +373,24 @@ class InOrderDynInst : public FastAlloc, public RefCounted // INSTRUCTION TYPES - Forward checks to StaticInst object. // //////////////////////////////////////////////////////////// - bool isNop() const { return staticInst->isNop(); } - bool isMemRef() const { return staticInst->isMemRef(); } - bool isLoad() const { return staticInst->isLoad(); } - bool isStore() const { return staticInst->isStore(); } + bool isNop() const { return staticInst->isNop(); } + bool isMemRef() const { return staticInst->isMemRef(); } + bool isLoad() const { return staticInst->isLoad(); } + bool isStore() const { return staticInst->isStore(); } bool isStoreConditional() const { return staticInst->isStoreConditional(); } bool isInstPrefetch() const { return staticInst->isInstPrefetch(); } bool isDataPrefetch() const { return staticInst->isDataPrefetch(); } bool isCopy() const { return staticInst->isCopy(); } - bool isInteger() const { return staticInst->isInteger(); } - bool isFloating() const { return staticInst->isFloating(); } - bool isControl() const { return staticInst->isControl(); } - bool isCall() const { return staticInst->isCall(); } - bool isReturn() const { return staticInst->isReturn(); } - bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } + bool isInteger() const { return staticInst->isInteger(); } + bool isFloating() const { return staticInst->isFloating(); } + bool isControl() const { return staticInst->isControl(); } + bool isCall() const { return staticInst->isCall(); } + bool isReturn() const { return staticInst->isReturn(); } + bool isDirectCtrl() const { return staticInst->isDirectCtrl(); } bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); } - bool isCondCtrl() const { return staticInst->isCondCtrl(); } - bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } + bool isCondCtrl() const { return staticInst->isCondCtrl(); } + bool isUncondCtrl() const { return staticInst->isUncondCtrl(); } bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } bool isThreadSync() const { return staticInst->isThreadSync(); } @@ -674,7 +674,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted // ////////////////////////////////////////////////// /** Returns the number of source registers. */ - int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } + int8_t numSrcRegs() const { return staticInst->numSrcRegs(); } /** Returns the number of destination registers. */ int8_t numDestRegs() const { return staticInst->numDestRegs(); } diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh index 06ef95e44..2e0143f9f 100644 --- a/src/cpu/inorder/resource.hh +++ b/src/cpu/inorder/resource.hh @@ -253,7 +253,7 @@ class ResourceEvent : public Event /// (for InOrderCPU model). /// check src/sim/eventq.hh for more event priorities. enum InOrderPriority { - Resource_Event_Pri = 45, + Resource_Event_Pri = 45, }; /** The Resource Slot that this event is servicing */ diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 49b394c61..af8c4892c 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -258,7 +258,7 @@ class CacheRequest : public ResourceRequest } virtual PacketDataPtr getData() - { return reqData; } + { return reqData; } void setMemAccCompleted(bool completed = true) -- cgit v1.2.3