From 6c5a3ab8b28ae14e1f1c37076b7370b37c70de62 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Wed, 2 Jan 2008 15:22:38 -0800 Subject: Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b --- src/cpu/memtest/memtest.cc | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc index 29da517b3..819b95e70 100644 --- a/src/cpu/memtest/memtest.cc +++ b/src/cpu/memtest/memtest.cc @@ -207,9 +207,9 @@ MemTest::completeRequest(PacketPtr pkt) assert(removeAddr != outstandingAddrs.end()); outstandingAddrs.erase(removeAddr); - switch (pkt->cmd.toInt()) { - case MemCmd::ReadResp: + assert(pkt->isResponse()); + if (pkt->isRead()) { if (memcmp(pkt_data, data, pkt->getSize()) != 0) { panic("%s: read of %x (blk %x) @ cycle %d " "returns %x, expected %x\n", name(), @@ -228,14 +228,9 @@ MemTest::completeRequest(PacketPtr pkt) if (maxLoads != 0 && numReads >= maxLoads) exitSimLoop("maximum number of loads reached"); - break; - - case MemCmd::WriteResp: + } else { + assert(pkt->isWrite()); numWritesStat++; - break; - - default: - panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt()); } noResponseCycles = 0; -- cgit v1.2.3