From 6d3200440702719356ee337fc7f24075cdb75224 Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Sat, 3 Jan 2015 17:51:48 -0600 Subject: minor: fixed LSQ MasterPortID Minor was reporting the data cache access as ".inst" accesses. This just switches the MasterPortID to dataMasterPortId. Committed by: Nilay Vaish --- src/cpu/minor/lsq.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index 501620746..49daa3518 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -1503,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0); request->request.setVirt(0 /* asid */, - addr, size, flags, cpu.instMasterId(), + addr, size, flags, cpu.dataMasterId(), /* I've no idea why we need the PC, but give it */ inst->pc.instAddr()); -- cgit v1.2.3