From 76c110d924d2adfa209ad4302af791dfe6f67946 Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Fri, 7 Jul 2006 15:16:41 -0400
Subject: Remove hack now that ports work properly

--HG--
extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
---
 src/cpu/simple/timing.cc | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 170c78d3a..12a47fb3e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -452,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    if (cpu->_status == DcacheWaitResponse)
-        cpu->completeDataAccess(pkt);
-    else if (cpu->_status == IcacheWaitResponse)
-        cpu->completeIfetch(pkt);
-    else
-        assert("OOPS" && 0);
+    cpu->completeIfetch(pkt);
     return true;
 }
 
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