From a1570f544f7eb24d87a664038705ae6801862eab Mon Sep 17 00:00:00 2001 From: Faissal Sleiman Date: Sat, 19 Apr 2014 09:00:30 -0500 Subject: o3: Fix occupancy checks for SMT A number of calls to isEmpty() and numFreeEntries() should be thread-specific. In cpu.cc, the fact that tid is /*commented*/ out is a bug. Say the rob has instructions from thread 0 (isEmpty() returns false), and none from thread 1. If we are trying to squash all of thread 1, then readTailInst(thread 1) will be called because rob->isEmpty() returns false. The result is end_it is not in the list and the while statement loops indefinitely back over the cpu's instList. In iew_impl.hh, all threads are told they have the entire remaining IQ, when each thread actually has a certain allocation. The result is extra stalls at the iew dispatch stage which the rename stage usually takes care of. In commit_impl.hh, rob->readHeadInst(thread 1) can be called if the rob only contains instructions from thread 0. This returns a dummyInst (which may work since we are trying to squash all instructions, but hardly seems like the right way to do it). In rob_impl.hh this fix skips the rest of the function more frequently and is more efficient. Committed by: Nilay Vaish --- src/cpu/o3/commit_impl.hh | 2 +- src/cpu/o3/cpu.cc | 2 +- src/cpu/o3/iew_impl.hh | 2 +- src/cpu/o3/rob_impl.hh | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 91e8e7681..5ca15f611 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -561,7 +561,7 @@ DefaultCommit::squashAll(ThreadID tid) // then use one older sequence number. // Hopefully this doesn't mess things up. Basically I want to squash // all instructions of this thread. - InstSeqNum squashed_inst = rob->isEmpty() ? + InstSeqNum squashed_inst = rob->isEmpty(tid) ? lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1; // All younger instructions will be squashed. Set the sequence diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 710482d3c..f87e6a923 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1640,7 +1640,7 @@ FullO3CPU::removeInstsNotInROB(ThreadID tid) if (instList.empty()) { return; - } else if (rob.isEmpty(/*tid*/)) { + } else if (rob.isEmpty(tid)) { DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); end_it = instList.begin(); rob_empty = true; diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 9cfbb3cfc..927a8d5a6 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1598,7 +1598,7 @@ DefaultIEW::tick() toRename->iewInfo[tid].usedIQ = true; toRename->iewInfo[tid].freeIQEntries = - instQueue.numFreeEntries(); + instQueue.numFreeEntries(tid); toRename->iewInfo[tid].usedLSQ = true; toRename->iewInfo[tid].freeLSQEntries = ldstQueue.numFreeEntries(tid); diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh index c047981a7..61d6bd11b 100644 --- a/src/cpu/o3/rob_impl.hh +++ b/src/cpu/o3/rob_impl.hh @@ -486,7 +486,7 @@ template void ROB::squash(InstSeqNum squash_num, ThreadID tid) { - if (isEmpty()) { + if (isEmpty(tid)) { DPRINTF(ROB, "Does not need to squash due to being empty " "[sn:%i]\n", squash_num); -- cgit v1.2.3