From a1aba01a02a8c1261120de83d8fbfd6624f0cb17 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:15:34 -0800 Subject: CPU: Get rid of translate... functions from various interface classes. --- src/cpu/base_dyn_inst.hh | 56 +--------------- src/cpu/checker/cpu.cc | 55 +--------------- src/cpu/checker/cpu.hh | 4 -- src/cpu/checker/cpu_impl.hh | 2 +- src/cpu/inorder/cpu.hh | 18 ------ src/cpu/inorder/resources/tlb_unit.cc | 6 +- src/cpu/o3/cpu.hh | 18 ------ src/cpu/o3/fetch_impl.hh | 2 +- src/cpu/ozone/cpu.hh | 47 ++------------ src/cpu/ozone/front_end_impl.hh | 2 +- src/cpu/ozone/inorder_back_end.hh | 4 +- src/cpu/simple/atomic.cc | 117 +-------------------------------- src/cpu/simple/atomic.hh | 5 -- src/cpu/simple/base.cc | 2 +- src/cpu/simple/timing.cc | 118 ++++++++++++++-------------------- src/cpu/simple/timing.hh | 6 -- src/cpu/simple_thread.hh | 15 ----- 17 files changed, 70 insertions(+), 407 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index f40616e54..f58bf7cf8 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -115,9 +115,6 @@ class BaseDynInst : public FastAlloc, public RefCounted template Fault read(Addr addr, T &data, unsigned flags); - Fault translateDataReadAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - /** * Does a write to a given address. * @param data The data to be written. @@ -130,9 +127,6 @@ class BaseDynInst : public FastAlloc, public RefCounted Fault write(T data, Addr addr, unsigned flags, uint64_t *res); - Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - void prefetch(Addr addr, unsigned flags); void writeHint(Addr addr, int size, unsigned flags); Fault copySrcTranslate(Addr src); @@ -856,29 +850,6 @@ class BaseDynInst : public FastAlloc, public RefCounted { thread->storeCondFailures = sc_failures; } }; -template -Fault -BaseDynInst::translateDataReadAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags) -{ - if (traceData) { - traceData->setAddr(vaddr); - } - - reqMade = true; - Request *req = new Request(); - req->setVirt(asid, vaddr, size, flags, PC); - req->setThreadContext(thread->contextId(), threadNumber); - - fault = cpu->translateDataReadReq(req, thread); - - if (fault == NoFault) - paddr = req->getPaddr(); - - delete req; - return fault; -} - template template inline Fault @@ -889,7 +860,7 @@ BaseDynInst::read(Addr addr, T &data, unsigned flags) req->setVirt(asid, addr, sizeof(T), flags, this->PC); req->setThreadContext(thread->contextId(), threadNumber); - fault = cpu->translateDataReadReq(req, thread); + fault = cpu->dtb->translate(req, thread->getTC(), false); if (req->isUncacheable()) isUncacheable = true; @@ -930,29 +901,6 @@ BaseDynInst::read(Addr addr, T &data, unsigned flags) return fault; } -template -Fault -BaseDynInst::translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags) -{ - if (traceData) { - traceData->setAddr(vaddr); - } - - reqMade = true; - Request *req = new Request(); - req->setVirt(asid, vaddr, size, flags, PC); - req->setThreadContext(thread->contextId(), threadNumber); - - fault = cpu->translateDataWriteReq(req, thread); - - if (fault == NoFault) - paddr = req->getPaddr(); - - delete req; - return fault; -} - template template inline Fault @@ -968,7 +916,7 @@ BaseDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res) req->setVirt(asid, addr, sizeof(T), flags, this->PC); req->setThreadContext(thread->contextId(), threadNumber); - fault = cpu->translateDataWriteReq(req, thread); + fault = cpu->dtb->translate(req, thread->getTC(), true); if (req->isUncacheable()) isUncacheable = true; diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index a6af98d66..e530e6014 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -159,7 +159,7 @@ CheckerCPU::read(Addr addr, T &data, unsigned flags) memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); // translate to physical address - translateDataReadReq(memReq); + dtb->translate(memReq, tc, false); PacketPtr pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast); @@ -229,7 +229,7 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC()); // translate to physical address - thread->translateDataWriteReq(memReq); + dtb->translate(memReq, tc, true); // Can compare the write data and result only if it's cacheable, // not a store conditional, or is a store conditional that @@ -324,57 +324,6 @@ CheckerCPU::dbg_vtophys(Addr addr) } #endif // FULL_SYSTEM -bool -CheckerCPU::translateInstReq(Request *req) -{ -#if FULL_SYSTEM - return (thread->translateInstReq(req) == NoFault); -#else - thread->translateInstReq(req); - return true; -#endif -} - -void -CheckerCPU::translateDataReadReq(Request *req) -{ - thread->translateDataReadReq(req); - - if (req->getVaddr() != unverifiedReq->getVaddr()) { - warn("%lli: Request virtual addresses do not match! Inst: %#x, " - "checker: %#x", - curTick, unverifiedReq->getVaddr(), req->getVaddr()); - handleError(); - } - req->setPaddr(unverifiedReq->getPaddr()); - - if (checkFlags(req)) { - warn("%lli: Request flags do not match! Inst: %#x, checker: %#x", - curTick, unverifiedReq->getFlags(), req->getFlags()); - handleError(); - } -} - -void -CheckerCPU::translateDataWriteReq(Request *req) -{ - thread->translateDataWriteReq(req); - - if (req->getVaddr() != unverifiedReq->getVaddr()) { - warn("%lli: Request virtual addresses do not match! Inst: %#x, " - "checker: %#x", - curTick, unverifiedReq->getVaddr(), req->getVaddr()); - handleError(); - } - req->setPaddr(unverifiedReq->getPaddr()); - - if (checkFlags(req)) { - warn("%lli: Request flags do not match! Inst: %#x, checker: %#x", - curTick, unverifiedReq->getFlags(), req->getFlags()); - handleError(); - } -} - bool CheckerCPU::checkFlags(Request *req) { diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 5b3c4582c..0d3dddded 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -331,10 +331,6 @@ class CheckerCPU : public BaseCPU this->dtb->demapPage(vaddr, asn); } - bool translateInstReq(Request *req); - void translateDataWriteReq(Request *req); - void translateDataReadReq(Request *req); - #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } void ev5_trap(Fault fault) { fault->invoke(tc); } diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 0428e8806..e1ecc151c 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -155,7 +155,7 @@ Checker::verify(DynInstPtr &completed_inst) fetch_PC, thread->contextId(), inst->threadNumber); - bool succeeded = translateInstReq(memReq); + bool succeeded = itb->translate(memReq, thread); if (!succeeded) { if (inst->getFault() == NoFault) { diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 6c1cdc9dc..4a7dfb404 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -498,24 +498,6 @@ class InOrderCPU : public BaseCPU /** Debug function to print all instructions on the list. */ void dumpInsts(); - /** Translates instruction requestion in syscall emulation mode. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data read request in syscall emulation mode. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data write request in syscall emulation mode. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - /** Forwards an instruction read to the appropriate data * resource (indexes into Resource Pool thru "dataPortIdx") */ diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc index 9b0decedb..4eeb4727b 100644 --- a/src/cpu/inorder/resources/tlb_unit.cc +++ b/src/cpu/inorder/resources/tlb_unit.cc @@ -98,7 +98,8 @@ TLBUnit::execute(int slot_idx) case FetchLookup: { tlb_req->fault = - this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]); + this->cpu->itb->translate(tlb_req->memReq, + cpu->thread[tid]->getTC()); if (tlb_req->fault != NoFault) { DPRINTF(Resource, "[tid:%i]: %s encountered while translating " @@ -128,7 +129,8 @@ TLBUnit::execute(int slot_idx) tid, seq_num, tlb_req->memReq->getVaddr()); tlb_req->fault = - this->cpu->translateInstReq(tlb_req->memReq, cpu->thread[tid]); + this->cpu->itb->translate(tlb_req->memReq, + cpu->thread[tid]->getTC()); if (tlb_req->fault != NoFault) { DPRINTF(Resource, "[tid:%i]: %s encountered while translating " diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d14001d0d..683e4284f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -279,24 +279,6 @@ class FullO3CPU : public BaseO3CPU this->dtb->demapPage(vaddr, asn); } - /** Translates instruction requestion. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return this->itb->translate(req, thread->getTC()); - } - - /** Translates data read request. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), false); - } - - /** Translates data write request. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), true); - } - /** Returns a specific port. */ Port *getPort(const std::string &if_name, int idx); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index cff6db299..4beb34a85 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -599,7 +599,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid memReq[tid] = mem_req; // Translate the instruction request. - fault = cpu->translateInstReq(mem_req, cpu->thread[tid]); + fault = cpu->itb->translate(mem_req, cpu->thread[tid]->getTC()); // In the case of faults, the fetch stage may need to stall and wait // for the ITB miss to be handled. diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 55ad7b3fb..0eb4b31f7 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -415,59 +415,20 @@ class OzoneCPU : public BaseCPU void demapPage(Addr vaddr, uint64_t asn) { - itb->demap(vaddr, asn); - dtb->demap(vaddr, asn); + cpu->itb->demap(vaddr, asn); + cpu->dtb->demap(vaddr, asn); } void demapInstPage(Addr vaddr, uint64_t asn) { - itb->demap(vaddr, asn); + cpu->itb->demap(vaddr, asn); } void demapDataPage(Addr vaddr, uint64_t asn) { - dtb->demap(vaddr, asn); + cpu->dtb->demap(vaddr, asn); } -#if FULL_SYSTEM - /** Translates instruction requestion. */ - Fault translateInstReq(RequestPtr &req, OzoneThreadState *thread) - { - return itb->translate(req, thread->getTC()); - } - - /** Translates data read request. */ - Fault translateDataReadReq(RequestPtr &req, OzoneThreadState *thread) - { - return dtb->translate(req, thread->getTC(), false); - } - - /** Translates data write request. */ - Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState *thread) - { - return dtb->translate(req, thread->getTC(), true); - } - -#else - /** Translates instruction requestion in syscall emulation mode. */ - Fault translateInstReq(RequestPtr &req, OzoneThreadState *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data read request in syscall emulation mode. */ - Fault translateDataReadReq(RequestPtr &req, OzoneThreadState *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data write request in syscall emulation mode. */ - Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } -#endif - /** CPU read function, forwards read to LSQ. */ template Fault read(Request *req, T &data, int load_idx) diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index b1e131115..2a9b107d4 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -480,7 +480,7 @@ FrontEnd::fetchCacheLine() PC, cpu->thread->contextId()); // Translate the instruction request. - fault = cpu->translateInstReq(memReq, thread); + fault = cpu->itb->translate(memReq, thread); // Now do the timing access to see whether or not the instruction // exists within the cache. diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh index c23d801ba..8850fa737 100644 --- a/src/cpu/ozone/inorder_back_end.hh +++ b/src/cpu/ozone/inorder_back_end.hh @@ -204,7 +204,7 @@ InorderBackEnd::read(Addr addr, T &data, unsigned flags) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->translateDataReadReq(memReq); + Fault fault = cpu->dtb->translate(memReq, thread->getTC(), false); // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { @@ -245,7 +245,7 @@ InorderBackEnd::write(T data, Addr addr, unsigned flags, uint64_t *res) memReq->reset(addr, sizeof(T), flags); // translate to physical address - Fault fault = cpu->translateDataWriteReq(memReq); + Fault fault = cpu->dtb->translate(memReq, thread->getTC(), true); if (fault == NoFault && dcacheInterface) { memReq->cmd = Write; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index feb8a7fc5..cd07a9fe3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) req->setVirt(0, addr, dataSize, flags, thread->readPC()); // translate to physical address - Fault fault = thread->translateDataReadReq(req); + Fault fault = thread->dtb->translate(req, tc, false); // Now do the access. if (fault == NoFault) { @@ -370,61 +370,6 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) } } -Fault -AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr, - int size, unsigned flags) -{ - // use the CPU's statically allocated read request and packet objects - Request *req = &data_read_req; - - if (traceData) { - traceData->setAddr(vaddr); - } - - //The block size of our peer. - int blockSize = dcachePort.peerBlockSize(); - //The size of the data we're trying to read. - int dataSize = size; - - bool firstTimeThrough = true; - - //The address of the second part of this access if it needs to be split - //across a cache line boundary. - Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize); - - if(secondAddr > vaddr) - dataSize = secondAddr - vaddr; - - while(1) { - req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); - - // translate to physical address - Fault fault = thread->translateDataReadReq(req); - - //If there's a fault, return it - if (fault != NoFault) - return fault; - - if (firstTimeThrough) { - paddr = req->getPaddr(); - firstTimeThrough = false; - } - - //If we don't need to access a second cache line, stop now. - if (secondAddr <= vaddr) - return fault; - - /* - * Set up for accessing the second cache line. - */ - - //Adjust the size to get the remaining bytes. - dataSize = vaddr + size - secondAddr; - //And access the right address. - vaddr = secondAddr; - } -} - #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -507,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) req->setVirt(0, addr, dataSize, flags, thread->readPC()); // translate to physical address - Fault fault = thread->translateDataWriteReq(req); + Fault fault = thread->dtb->translate(req, tc, true); // Now do the access. if (fault == NoFault) { @@ -586,64 +531,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) } } -Fault -AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags) -{ - // use the CPU's statically allocated write request and packet objects - Request *req = &data_write_req; - - if (traceData) { - traceData->setAddr(vaddr); - } - - //The block size of our peer. - int blockSize = dcachePort.peerBlockSize(); - - //The address of the second part of this access if it needs to be split - //across a cache line boundary. - Addr secondAddr = roundDown(vaddr + size - 1, blockSize); - - //The size of the data we're trying to read. - int dataSize = size; - - bool firstTimeThrough = true; - - if(secondAddr > vaddr) - dataSize = secondAddr - vaddr; - - dcache_latency = 0; - - while(1) { - req->setVirt(0, vaddr, dataSize, flags, thread->readPC()); - - // translate to physical address - Fault fault = thread->translateDataWriteReq(req); - - //If there's a fault or we don't need to access a second cache line, - //stop now. - if (fault != NoFault) - return fault; - - if (firstTimeThrough) { - paddr = req->getPaddr(); - firstTimeThrough = false; - } - - if (secondAddr <= vaddr) - return fault; - - /* - * Set up for accessing the second cache line. - */ - - //Adjust the size to get the remaining bytes. - dataSize = vaddr + size - secondAddr; - //And access the right address. - vaddr = secondAddr; - } -} - #ifndef DOXYGEN_SHOULD_SKIP_THIS diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 24400df22..190097637 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -136,11 +136,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU template Fault write(T data, Addr addr, unsigned flags, uint64_t *res); - Fault translateDataReadAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - /** * Print state of address in memory system via PrintReq (for * debugging). diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index b1a77247f..f9fa8d835 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req) Addr fetchPC = (threadPC & PCMask) + fetchOffset; req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC); - Fault fault = thread->translateInstReq(req); + Fault fault = thread->itb->translate(req, tc); return fault; } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 5da08db47..844eccc75 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -275,6 +275,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, if ((fault = buildPacket(pkt1, req1, read)) != NoFault || (fault = buildPacket(pkt2, req2, read)) != NoFault) { delete req; + delete req1; delete pkt1; req = NULL; pkt1 = NULL; @@ -286,6 +287,15 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), Packet::Broadcast); + if (req->getFlags().isSet(Request::NO_ACCESS)) { + delete req1; + delete pkt1; + delete req2; + delete pkt2; + pkt1 = pkt; + pkt2 = NULL; + return NoFault; + } pkt->dataDynamic(data); pkt1->dataStatic(data); @@ -304,8 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, Fault TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read) { - Fault fault = read ? thread->translateDataReadReq(req) : - thread->translateDataWriteReq(req); + Fault fault = thread->dtb->translate(req, tc, !read); MemCmd cmd; if (fault != NoFault) { delete req; @@ -348,9 +357,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) if (split_addr > addr) { PacketPtr pkt1, pkt2; - this->buildSplitPacket(pkt1, pkt2, req, + Fault fault = this->buildSplitPacket(pkt1, pkt2, req, split_addr, (uint8_t *)(new T), true); - if (handleReadPacket(pkt1)) { + if (fault != NoFault) + return fault; + if (req->getFlags().isSet(Request::NO_ACCESS)) { + dcache_pkt = pkt1; + } else if (handleReadPacket(pkt1)) { SplitFragmentSenderState * send_state = dynamic_cast(pkt1->senderState); send_state->clearFromParent(); @@ -365,9 +378,12 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) if (fault != NoFault) { return fault; } - pkt->dataDynamic(new T); - - handleReadPacket(pkt); + if (req->getFlags().isSet(Request::NO_ACCESS)) { + dcache_pkt = pkt; + } else { + pkt->dataDynamic(new T); + handleReadPacket(pkt); + } } if (traceData) { @@ -382,26 +398,6 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) return NoFault; } -Fault -TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags) -{ - Request *req = - new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); - - if (traceData) { - traceData->setAddr(vaddr); - } - - Fault fault = thread->translateDataWriteReq(req); - - if (fault == NoFault) - paddr = req->getPaddr(); - - delete req; - return fault; -} - #ifndef DOXYGEN_SHOULD_SKIP_THIS template @@ -497,15 +493,19 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (fault != NoFault) return fault; dcache_pkt = pkt1; - if (handleWritePacket()) { - SplitFragmentSenderState * send_state = - dynamic_cast(pkt1->senderState); - send_state->clearFromParent(); - dcache_pkt = pkt2; - if (handleReadPacket(pkt2)) { - send_state = - dynamic_cast(pkt1->senderState); + if (!req->getFlags().isSet(Request::NO_ACCESS)) { + if (handleWritePacket()) { + SplitFragmentSenderState * send_state = + dynamic_cast( + pkt1->senderState); send_state->clearFromParent(); + dcache_pkt = pkt2; + if (handleReadPacket(pkt2)) { + send_state = + dynamic_cast( + pkt1->senderState); + send_state->clearFromParent(); + } } } } else { @@ -515,21 +515,23 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) if (fault != NoFault) return fault; - if (req->isLocked()) { - do_access = TheISA::handleLockedWrite(thread, req); - } else if (req->isCondSwap()) { - assert(res); - req->setExtraData(*res); - } + if (!req->getFlags().isSet(Request::NO_ACCESS)) { + if (req->isLocked()) { + do_access = TheISA::handleLockedWrite(thread, req); + } else if (req->isCondSwap()) { + assert(res); + req->setExtraData(*res); + } - dcache_pkt->allocate(); - if (req->isMmapedIpr()) - dcache_pkt->set(htog(data)); - else - dcache_pkt->set(data); + dcache_pkt->allocate(); + if (req->isMmapedIpr()) + dcache_pkt->set(htog(data)); + else + dcache_pkt->set(data); - if (do_access) - handleWritePacket(); + if (do_access) + handleWritePacket(); + } } if (traceData) { @@ -546,26 +548,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) return NoFault; } -Fault -TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags) -{ - Request *req = - new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); - - if (traceData) { - traceData->setAddr(vaddr); - } - - Fault fault = thread->translateDataWriteReq(req); - - if (fault == NoFault) - paddr = req->getPaddr(); - - delete req; - return fault; -} - #ifndef DOXYGEN_SHOULD_SKIP_THIS template diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index c305d0361..0a639a627 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -224,15 +224,9 @@ class TimingSimpleCPU : public BaseSimpleCPU template Fault read(Addr addr, T &data, unsigned flags); - Fault translateDataReadAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - template Fault write(T data, Addr addr, unsigned flags, uint64_t *res); - Fault translateDataWriteAddr(Addr vaddr, Addr &paddr, - int size, unsigned flags); - void fetch(); void completeIfetch(PacketPtr ); void completeDataAccess(PacketPtr ); diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 678bb42bb..c2ddeca06 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -148,21 +148,6 @@ class SimpleThread : public ThreadState */ ThreadContext *getTC() { return tc; } - Fault translateInstReq(RequestPtr &req) - { - return itb->translate(req, tc); - } - - Fault translateDataReadReq(RequestPtr &req) - { - return dtb->translate(req, tc, false); - } - - Fault translateDataWriteReq(RequestPtr &req) - { - return dtb->translate(req, tc, true); - } - void demapPage(Addr vaddr, uint64_t asn) { itb->demapPage(vaddr, asn); -- cgit v1.2.3