From f78bc80bd75f6f4ebf080620b3aaeaee3b3e46cc Mon Sep 17 00:00:00 2001
From: Steve Reinhardt <stever@eecs.umich.edu>
Date: Mon, 12 Feb 2007 09:26:47 -0800
Subject: Move store conditional result checking from SimpleAtomicCpu write
 function into Alpha ISA description.  write now just generically returns a
 result value if the res pointer is non-null (which means we can only provide
 a res pointer if we expect a valid result value).

--HG--
extra : convert_revision : fb1c315515787f5fbbf7d1af7e428bdbfe8148b8
---
 src/cpu/simple/atomic.cc | 11 ++---------
 src/cpu/simple/base.hh   |  8 ++++++++
 2 files changed, 10 insertions(+), 9 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index fa47b0eee..6a536fbcd 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -401,15 +401,8 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 #endif
         }
 
-        if (req->isLocked()) {
-            uint64_t scResult = req->getScResult();
-            if (scResult != 0) {
-                // clear failure counter
-                thread->setStCondFailures(0);
-            }
-            if (res) {
-                *res = req->getScResult();
-            }
+        if (res) {
+            *res = req->getScResult();
         }
     }
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index c4853b916..a2b624139 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -329,6 +329,14 @@ class BaseSimpleCPU : public BaseCPU
         return thread->setMiscRegWithEffect(reg_idx, val);
     }
 
+    unsigned readStCondFailures() {
+        return thread->readStCondFailures();
+    }
+
+    void setStCondFailures(unsigned sc_failures) {
+        thread->setStCondFailures(sc_failures);
+    }
+
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
-- 
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