From 4862879a9420c52d48532d957b616c458b643a1e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 02:08:44 -0500 Subject: Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes more neutral names. --HG-- extra : convert_revision : 702c715b7516a16602172deb1b78d6a7ab848fd4 --- src/cpu/simple/atomic.cc | 4 ++-- src/cpu/simple/base.hh | 11 +++++++---- src/cpu/simple/timing.cc | 4 ++-- src/cpu/simple_thread.cc | 2 +- src/cpu/simple_thread.hh | 10 +++++----- src/cpu/thread_context.hh | 17 ++++++++++------- 6 files changed, 27 insertions(+), 21 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 11e4d2acb..1e12aadef 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -513,8 +513,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) Param cpu_id; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; Param profile; #else SimObjectParam workload; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index af6b6f835..1a9fc5127 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -47,8 +47,11 @@ // forward declarations #if FULL_SYSTEM class Processor; -class AlphaITB; -class AlphaDTB; +namespace TheISA +{ + class ITB; + class DTB; +} class MemObject; class RemoteGDB; @@ -97,8 +100,8 @@ class BaseSimpleCPU : public BaseCPU { MemObject *mem; #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #else Process *process; #endif diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fe6775ea4..438417882 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -665,8 +665,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) Param cpu_id; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; Param profile; #else SimObjectParam workload; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 4fc47c982..95018ff8c 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -60,7 +60,7 @@ using namespace std; // constructor #if FULL_SYSTEM SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, - AlphaITB *_itb, AlphaDTB *_dtb, + TheISA::ITB *_itb, TheISA::DTB *_dtb, bool use_kernel_stats) : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fe22e6c43..10ec8faaa 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -107,14 +107,14 @@ class SimpleThread : public ThreadState System *system; #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #endif // constructor: initialize SimpleThread from given process structure #if FULL_SYSTEM SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, - AlphaITB *_itb, AlphaDTB *_dtb, + TheISA::ITB *_itb, TheISA::DTB *_dtb, bool use_kernel_stats = true); #else SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, @@ -201,9 +201,9 @@ class SimpleThread : public ThreadState #if FULL_SYSTEM System *getSystemPtr() { return system; } - AlphaITB *getITBPtr() { return itb; } + TheISA::ITB *getITBPtr() { return itb; } - AlphaDTB *getDTBPtr() { return dtb; } + TheISA::DTB *getDTBPtr() { return dtb; } FunctionalPort *getPhysPort() { return physPort; } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 73046097d..448d67d02 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -31,9 +31,9 @@ #ifndef __CPU_THREAD_CONTEXT_HH__ #define __CPU_THREAD_CONTEXT_HH__ -#include "arch/types.hh" #include "arch/regfile.hh" #include "arch/syscallreturn.hh" +#include "arch/types.hh" #include "config/full_system.hh" #include "mem/request.hh" #include "sim/faults.hh" @@ -43,8 +43,11 @@ // @todo: Figure out a more architecture independent way to obtain the ITB and // DTB pointers. -class AlphaDTB; -class AlphaITB; +namespace TheISA +{ + class DTB; + class ITB; +} class BaseCPU; class EndQuiesceEvent; class Event; @@ -117,9 +120,9 @@ class ThreadContext #if FULL_SYSTEM virtual System *getSystemPtr() = 0; - virtual AlphaITB *getITBPtr() = 0; + virtual TheISA::ITB *getITBPtr() = 0; - virtual AlphaDTB * getDTBPtr() = 0; + virtual TheISA::DTB *getDTBPtr() = 0; virtual Kernel::Statistics *getKernelStats() = 0; @@ -292,9 +295,9 @@ class ProxyThreadContext : public ThreadContext #if FULL_SYSTEM System *getSystemPtr() { return actualTC->getSystemPtr(); } - AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } + TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } - AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } + TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } -- cgit v1.2.3 From 038217049a952a67f29b79c416a35d89fea31f70 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 03:37:01 -0500 Subject: Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9 --- src/cpu/checker/cpu.hh | 2 -- src/cpu/exec_context.hh | 4 ---- src/cpu/o3/alpha/cpu.hh | 4 ---- src/cpu/o3/alpha/cpu_impl.hh | 14 -------------- src/cpu/o3/alpha/dyn_inst_impl.hh | 14 -------------- src/cpu/o3/regfile.hh | 6 ------ src/cpu/ozone/cpu.hh | 2 -- src/cpu/ozone/dyn_inst.hh | 2 -- src/cpu/ozone/dyn_inst_impl.hh | 14 -------------- src/cpu/simple/base.hh | 2 -- src/cpu/simple_thread.hh | 2 -- 11 files changed, 66 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 00b01171f..7c01bdc39 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -328,8 +328,6 @@ class CheckerCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - int readIntrFlag() { return thread->readIntrFlag(); } - void setIntrFlag(int val) { thread->setIntrFlag(val); } bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index f6e8d7c25..e28b33193 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -144,10 +144,6 @@ class ExecContext { /** Somewhat Alpha-specific function that handles returning from * an error or interrupt. */ Fault hwrei(); - /** Reads the interrupt flags. */ - int readIntrFlag(); - /** Sets the interrupt flags to a value. */ - void setIntrFlag(int val); /** * Check for special simulator handling of specific PAL calls. If diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 9d97f9701..474fce02a 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU #if FULL_SYSTEM /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - /** Reads the interrupt flag. */ - int readIntrFlag(); - /** Sets the interrupt flags. */ - void setIntrFlag(int val); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); /** Returns if a specific PC is a PAL mode PC. */ diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index b7362fad9..a57c5d9ed 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -241,20 +241,6 @@ AlphaO3CPU::post_interrupt(int int_num, int index) } } -template -int -AlphaO3CPU::readIntrFlag() -{ - return this->regFile.readIntrFlag(); -} - -template -void -AlphaO3CPU::setIntrFlag(int val) -{ - this->regFile.setIntrFlag(val); -} - template Fault AlphaO3CPU::hwrei(unsigned tid) diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index b273a7b9b..f27cd5961 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -127,20 +127,6 @@ AlphaDynInst::hwrei() return NoFault; } -template -int -AlphaDynInst::readIntrFlag() -{ - return this->cpu->readIntrFlag(); -} - -template -void -AlphaDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool AlphaDynInst::inPalMode() diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 512cf0721..10f6db390 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -251,12 +251,6 @@ class PhysRegFile cpu->tcBase(thread_id)); } -#if FULL_SYSTEM - int readIntrFlag() { return intrflag; } - /** Sets an interrupt flag. */ - void setIntrFlag(int val) { intrflag = val; } -#endif - public: /** (signed) integer register file. */ IntReg *intRegFile; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 70ec1d101..bd46b198b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag() { return thread.intrflag; } - void setIntrFlag(int val) { thread.intrflag = val; } bool inPalMode() { return AlphaISA::PcPAL(thread.PC); } bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); } bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index e7390626e..d3871568a 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst #if FULL_SYSTEM Fault hwrei(); - int readIntrFlag(); - void setIntrFlag(int val); bool inPalMode(); void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 9d42ab05b..d86f2dc8b 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -260,20 +260,6 @@ OzoneDynInst::hwrei() return NoFault; } -template -int -OzoneDynInst::readIntrFlag() -{ -return this->cpu->readIntrFlag(); -} - -template -void -OzoneDynInst::setIntrFlag(int val) -{ - this->cpu->setIntrFlag(val); -} - template bool OzoneDynInst::inPalMode() diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 1a9fc5127..1d208b8df 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -305,8 +305,6 @@ class BaseSimpleCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - int readIntrFlag() { return thread->readIntrFlag(); } - void setIntrFlag(int val) { thread->setIntrFlag(val); } bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 10ec8faaa..d005b2914 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -168,8 +168,6 @@ class SimpleThread : public ThreadState void dumpFuncProfile(); - int readIntrFlag() { return regs.intrflag; } - void setIntrFlag(int val) { regs.intrflag = val; } Fault hwrei(); bool simPalCheck(int palFunc); -- cgit v1.2.3 From 3c19c5f0f239b8d31a3a8acd03eff9923f19b6ee Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 31 Oct 2006 04:12:52 -0500 Subject: Missed a few instances of this function. --HG-- extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622 --- src/cpu/o3/alpha/dyn_inst.hh | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 294aadde8..31a6f7753 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -127,10 +127,6 @@ class AlphaDynInst : public BaseDynInst #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Reads interrupt flag. */ - int readIntrFlag(); - /** Sets interrupt flag. */ - void setIntrFlag(int val); /** Checks if system is in PAL mode. */ bool inPalMode(); /** Traps to handle specified fault. */ -- cgit v1.2.3 From b26355daa87c7a86a96a90b2002bc5684741288c Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 13:59:30 -0500 Subject: Ports now have a pointer to the MemObject that owns it (can be NULL). src/cpu/simple/atomic.hh: Port now takes in the MemObject that owns it. src/cpu/simple/timing.hh: Port now takes in MemObject that owns it. src/dev/io_device.cc: src/mem/bus.hh: Ports now take in the MemObject that owns it. src/mem/cache/base_cache.cc: Ports now take in the MemObject that own it. src/mem/port.hh: src/mem/tport.hh: Ports now optionally take in the MemObject that owns it. --HG-- extra : convert_revision : 890a72a871795987c2236c65937e06973412d349 --- src/cpu/simple/atomic.hh | 2 +- src/cpu/simple/timing.hh | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 0edca9369..166a18127 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -87,7 +87,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU public: CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu) - : Port(_name), cpu(_cpu) + : Port(_name, _cpu), cpu(_cpu) { } protected: diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 577e13e40..408fa315e 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -79,7 +79,7 @@ class TimingSimpleCPU : public BaseSimpleCPU public: CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat) - : Port(_name), cpu(_cpu), lat(_lat) + : Port(_name, _cpu), cpu(_cpu), lat(_lat) { } protected: @@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU PacketPtr ifetch_pkt; PacketPtr dcache_pkt; + + int cpu_id; Tick previousTick; -- cgit v1.2.3 From bfd5eb2b08dad700d085a637d5e16a61dcc530d7 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 31 Oct 2006 14:33:56 -0500 Subject: Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3 --- src/cpu/checker/cpu.cc | 20 ++++++------------- src/cpu/checker/cpu.hh | 4 ---- src/cpu/memtest/memtest.hh | 2 +- src/cpu/o3/alpha/cpu_builder.cc | 6 ------ src/cpu/o3/alpha/cpu_impl.hh | 18 ++--------------- src/cpu/o3/cpu.cc | 2 -- src/cpu/o3/cpu.hh | 3 --- src/cpu/o3/fetch.hh | 2 -- src/cpu/o3/fetch_impl.hh | 3 +-- src/cpu/o3/mips/cpu_builder.cc | 6 ------ src/cpu/o3/mips/cpu_impl.hh | 18 ++--------------- src/cpu/o3/params.hh | 2 -- src/cpu/o3/thread_state.hh | 7 +++---- src/cpu/ozone/cpu.hh | 2 -- src/cpu/ozone/cpu_builder.cc | 5 ----- src/cpu/ozone/cpu_impl.hh | 19 +++--------------- src/cpu/ozone/front_end.hh | 2 -- src/cpu/ozone/front_end_impl.hh | 1 - src/cpu/ozone/lw_lsq.hh | 2 -- src/cpu/ozone/lw_lsq_impl.hh | 2 -- src/cpu/ozone/simple_params.hh | 2 -- src/cpu/ozone/thread_state.hh | 6 +++--- src/cpu/simple/atomic.cc | 12 ------------ src/cpu/simple/base.cc | 4 ++-- src/cpu/simple/base.hh | 3 --- src/cpu/simple/timing.cc | 3 --- src/cpu/simple_thread.cc | 38 ++++++++++++++++++++++-------------- src/cpu/simple_thread.hh | 6 ++++-- src/cpu/thread_state.cc | 43 +++++++++++++++++++++++++++++++++++------ src/cpu/thread_state.hh | 14 +++++++++----- 30 files changed, 97 insertions(+), 160 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 9cb6b032e..2e81b7b31 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -72,6 +72,12 @@ CheckerCPU::CheckerCPU(Params *p) systemPtr = NULL; #else process = p->process; + thread = new SimpleThread(this, /* thread_num */ 0, process, + /* asid */ 0); + + thread->setStatus(ThreadContext::Suspended); + tc = thread->getTC(); + threadContexts.push_back(tc); #endif result.integer = 0; @@ -81,20 +87,6 @@ CheckerCPU::~CheckerCPU() { } -void -CheckerCPU::setMemory(MemObject *mem) -{ -#if !FULL_SYSTEM - memPtr = mem; - thread = new SimpleThread(this, /* thread_num */ 0, process, - /* asid */ 0, mem); - - thread->setStatus(ThreadContext::Suspended); - tc = thread->getTC(); - threadContexts.push_back(tc); -#endif -} - void CheckerCPU::setSystem(System *system) { diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 00b01171f..336cb1714 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -112,10 +112,6 @@ class CheckerCPU : public BaseCPU Process *process; - void setMemory(MemObject *mem); - - MemObject *memPtr; - void setSystem(System *system); System *systemPtr; diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh index edde4a3b2..2694efd39 100644 --- a/src/cpu/memtest/memtest.hh +++ b/src/cpu/memtest/memtest.hh @@ -97,7 +97,7 @@ class MemTest : public MemObject public: CpuPort(const std::string &_name, MemTest *_memtest) - : Port(_name), memtest(_memtest) + : Port(_name, _memtest), memtest(_memtest) { } protected: diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index ff123a6f7..ca316433b 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -61,8 +61,6 @@ Param profile; SimObjectVectorParam workload; #endif // FULL_SYSTEM -SimObjectParam mem; - SimObjectParam checker; Param max_insts_any_thread; @@ -169,8 +167,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), #endif // FULL_SYSTEM - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -314,8 +310,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; #endif // FULL_SYSTEM - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index b7362fad9..5deee27de 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -77,24 +77,10 @@ AlphaO3CPU::AlphaO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); -#if !FULL_SYSTEM - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); -#endif //usedTids[i] = true; //threadMap[i] = i; } else { @@ -102,7 +88,7 @@ AlphaO3CPU::AlphaO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } #endif // !FULL_SYSTEM diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 367508288..dfe42d882 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -187,7 +187,6 @@ FullO3CPU::FullO3CPU(Params *params) system(params->system), physmem(system->physmem), #endif // FULL_SYSTEM - mem(params->mem), drainCount(0), deferRegistration(params->deferRegistration), numThreads(number_of_threads) @@ -204,7 +203,6 @@ FullO3CPU::FullO3CPU(Params *params) #if USE_CHECKER BaseCPU *temp_checker = params->checker; checker = dynamic_cast *>(temp_checker); - checker->setMemory(mem); #if FULL_SYSTEM checker->setSystem(params->system); #endif diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index fe510519c..2bf9cb23b 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -620,9 +620,6 @@ class FullO3CPU : public BaseO3CPU PhysicalMemory *physmem; #endif - /** Pointer to memory. */ - MemObject *mem; - /** Event to call process() on once draining has completed. */ Event *drainEvent; diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 5555bff85..cc9a8abf5 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -329,8 +329,6 @@ class DefaultFetch /** Wire used to write any information heading to decode. */ typename TimeBuffer::wire toDecode; - MemObject *mem; - /** Icache interface. */ IcachePort *icachePort; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index e7bf83b20..2b152e376 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -96,8 +96,7 @@ DefaultFetch::IcachePort::recvRetry() template DefaultFetch::DefaultFetch(Params *params) - : mem(params->mem), - branchPred(params), + : branchPred(params), decodeToFetchDelay(params->decodeToFetchDelay), renameToFetchDelay(params->renameToFetchDelay), iewToFetchDelay(params->iewToFetchDelay), diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc index f1c3b33a5..ee9f2b48d 100644 --- a/src/cpu/o3/mips/cpu_builder.cc +++ b/src/cpu/o3/mips/cpu_builder.cc @@ -54,8 +54,6 @@ Param activity; SimObjectVectorParam workload; -SimObjectParam mem; - SimObjectParam checker; Param max_insts_any_thread; @@ -153,8 +151,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) INIT_PARAM(workload, "Processes to run"), - INIT_PARAM(mem, "Memory"), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -284,8 +280,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->workload = workload; - params->mem = mem; - params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index e08741626..97116fd3e 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -58,24 +58,10 @@ MipsO3CPU::MipsO3CPU(Params *params) if (i < params->workload.size()) { DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); - this->thread[i] = new Thread(this, i, params->workload[i], - i, params->mem); + this->thread[i] = new Thread(this, i, params->workload[i], i); this->thread[i]->setStatus(ThreadContext::Suspended); - - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), i), - params->workload[i]->pTable, - false); - mem_port = params->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - this->thread[i]->setMemPort(trans_port); - //usedTids[i] = true; //threadMap[i] = i; } else { @@ -83,7 +69,7 @@ MipsO3CPU::MipsO3CPU(Params *params) //when scheduling threads to CPU Process* dummy_proc = NULL; - this->thread[i] = new Thread(this, i, dummy_proc, i, params->mem); + this->thread[i] = new Thread(this, i, dummy_proc, i); //usedTids[i] = false; } diff --git a/src/cpu/o3/params.hh b/src/cpu/o3/params.hh index 1c234bcd7..b487778c6 100755 --- a/src/cpu/o3/params.hh +++ b/src/cpu/o3/params.hh @@ -54,8 +54,6 @@ class O3Params : public BaseO3CPU::Params Process *process; #endif // FULL_SYSTEM - MemObject *mem; - BaseCPU *checker; // diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 5fe7bb94d..d8720b3ab 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -77,7 +77,7 @@ struct O3ThreadState : public ThreadState { #if FULL_SYSTEM O3ThreadState(O3CPU *_cpu, int _thread_num) - : ThreadState(-1, _thread_num), + : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { @@ -95,9 +95,8 @@ struct O3ThreadState : public ThreadState { profilePC = 3; } #else - O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid, - MemObject *mem) - : ThreadState(-1, _thread_num, _process, _asid, mem), + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) { } #endif diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 70ec1d101..28ff8e9ba 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -368,8 +368,6 @@ class OzoneCPU : public BaseCPU virtual Port *getPort(const std::string &name, int idx); - MemObject *mem; - FrontEnd *frontEnd; BackEnd *backEnd; diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 730158258..39be9fd74 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -69,8 +69,6 @@ SimObjectVectorParam workload; //SimObjectParam page_table; #endif // FULL_SYSTEM -SimObjectParam mem; - SimObjectParam checker; Param max_insts_any_thread; @@ -191,8 +189,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) // INIT_PARAM(page_table, "Page table"), #endif // FULL_SYSTEM - INIT_PARAM_DFLT(mem, "Memory", NULL), - INIT_PARAM_DFLT(checker, "Checker CPU", NULL), INIT_PARAM_DFLT(max_insts_any_thread, @@ -350,7 +346,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) // params->pTable = page_table; #endif // FULL_SYSTEM - params->mem = mem; params->checker = checker; params->max_insts_any_thread = max_insts_any_thread; params->max_insts_all_threads = max_insts_all_threads; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index bf547bf94..685bf3cb4 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -93,10 +93,10 @@ OzoneCPU::OzoneCPU(Params *p) #if FULL_SYSTEM : BaseCPU(p), thread(this, 0), tickEvent(this, p->width), #else - : BaseCPU(p), thread(this, 0, p->workload[0], 0, p->mem), + : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width), #endif - mem(p->mem), comm(5, 5) + comm(5, 5) { frontEnd = new FrontEnd(p); backEnd = new BackEnd(p); @@ -107,7 +107,6 @@ OzoneCPU::OzoneCPU(Params *p) #if USE_CHECKER BaseCPU *temp_checker = p->checker; checker = dynamic_cast *>(temp_checker); - checker->setMemory(mem); #if FULL_SYSTEM checker->setSystem(p->system); #endif @@ -198,19 +197,7 @@ OzoneCPU::OzoneCPU(Params *p) frontEnd->renameTable.copyFrom(thread.renameTable); backEnd->renameTable.copyFrom(thread.renameTable); -#if !FULL_SYSTEM - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - TranslatingPort *trans_port; - trans_port = new TranslatingPort(csprintf("%s-%d-funcport", - name(), 0), - p->workload[0]->pTable, - false); - mem_port = p->mem->getPort("functional"); - mem_port->setPeer(trans_port); - trans_port->setPeer(mem_port); - thread.setMemPort(trans_port); -#else +#if FULL_SYSTEM Port *mem_port; FunctionalPort *phys_port; VirtualPort *virt_port; diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh index 2bdca35b9..e09e4de9c 100644 --- a/src/cpu/ozone/front_end.hh +++ b/src/cpu/ozone/front_end.hh @@ -208,8 +208,6 @@ class FrontEnd IcachePort icachePort; - MemObject *mem; - RequestPtr memReq; /** Mask to get a cache block's address. */ diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 36e87ec9c..b8fce4292 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -91,7 +91,6 @@ template FrontEnd::FrontEnd(Params *params) : branchPred(params), icachePort(this), - mem(params->mem), numInstsReady(params->frontEndLatency, 0), instBufferSize(0), maxInstBufferSize(params->maxInstBufferSize), diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh index dc58a8285..7e6849668 100644 --- a/src/cpu/ozone/lw_lsq.hh +++ b/src/cpu/ozone/lw_lsq.hh @@ -239,8 +239,6 @@ class OzoneLWLSQ { /** Pointer to the back-end stage. */ BackEnd *be; - MemObject *mem; - class DcachePort : public Port { protected: diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 1f3f18502..ee1968626 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -154,8 +154,6 @@ OzoneLWLSQ::init(Params *params, unsigned maxLQEntries, SQIndices.push(i); } - mem = params->mem; - usedPorts = 0; cachePorts = params->cachePorts; diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh index 3f63d2e1d..3e554c812 100644 --- a/src/cpu/ozone/simple_params.hh +++ b/src/cpu/ozone/simple_params.hh @@ -61,8 +61,6 @@ class SimpleParams : public BaseCPU::Params //Page Table PageTable *pTable; - MemObject *mem; - // // Caches // diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index c86f3552e..c226d7502 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -67,7 +67,7 @@ struct OzoneThreadState : public ThreadState { #if FULL_SYSTEM OzoneThreadState(CPUType *_cpu, int _thread_num) - : ThreadState(-1, _thread_num), + : ThreadState(_cpu, -1, _thread_num), intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { @@ -87,8 +87,8 @@ struct OzoneThreadState : public ThreadState { } #else OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process, - int _asid, MemObject *mem) - : ThreadState(-1, _thread_num, _process, _asid, mem), + int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) { miscRegFile.clear(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index edba55b0d..bfb80dc0f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -72,15 +72,6 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx) void AtomicSimpleCPU::init() { - //Create Memory Ports (conect them up) -// Port *mem_dport = mem->getPort(""); -// dcachePort.setPeer(mem_dport); -// mem_dport->setPeer(&dcachePort); - -// Port *mem_iport = mem->getPort(""); -// icachePort.setPeer(mem_iport); -// mem_iport->setPeer(&icachePort); - BaseCPU::init(); #if FULL_SYSTEM for (int i = 0; i < threadContexts.size(); ++i) { @@ -500,7 +491,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU) Param max_loads_any_thread; Param max_loads_all_threads; Param progress_interval; - SimObjectParam mem; SimObjectParam system; Param cpu_id; @@ -533,7 +523,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU) INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), INIT_PARAM(progress_interval, "Progress interval"), - INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), INIT_PARAM(cpu_id, "processor ID"), @@ -571,7 +560,6 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU) params->functionTraceStart = function_trace_start; params->width = width; params->simulate_stalls = simulate_stalls; - params->mem = mem; params->system = system; params->cpu_id = cpu_id; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index cbb3980cb..dc06c17f5 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -70,13 +70,13 @@ using namespace std; using namespace TheISA; BaseSimpleCPU::BaseSimpleCPU(Params *p) - : BaseCPU(p), mem(p->mem), thread(NULL) + : BaseCPU(p), thread(NULL) { #if FULL_SYSTEM thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb); #else thread = new SimpleThread(this, /* thread_num */ 0, p->process, - /* asid */ 0, mem); + /* asid */ 0); #endif // !FULL_SYSTEM thread->setStatus(ThreadContext::Suspended); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index af6b6f835..f382158dd 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -76,8 +76,6 @@ class BaseSimpleCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - MemObject *mem; - protected: Trace::InstRecord *traceData; @@ -95,7 +93,6 @@ class BaseSimpleCPU : public BaseCPU public: struct Params : public BaseCPU::Params { - MemObject *mem; #if FULL_SYSTEM AlphaITB *itb; AlphaDTB *dtb; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index fe6775ea4..9e1f091b5 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -660,7 +660,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) Param max_loads_any_thread; Param max_loads_all_threads; Param progress_interval; - SimObjectParam mem; SimObjectParam system; Param cpu_id; @@ -693,7 +692,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU) INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), INIT_PARAM(progress_interval, "Progress interval"), - INIT_PARAM(mem, "memory"), INIT_PARAM(system, "system object"), INIT_PARAM(cpu_id, "processor ID"), @@ -729,7 +727,6 @@ CREATE_SIM_OBJECT(TimingSimpleCPU) params->clock = clock; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; - params->mem = mem; params->system = system; params->cpu_id = cpu_id; diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 4fc47c982..c89a13eef 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -62,7 +62,7 @@ using namespace std; SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, AlphaITB *_itb, AlphaDTB *_dtb, bool use_kernel_stats) - : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), + : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) { @@ -106,19 +106,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, } #else SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, - Process *_process, int _asid, MemObject* memobj) - : ThreadState(-1, _thread_num, _process, _asid, memobj), + Process *_process, int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu) { - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - port = new TranslatingPort(csprintf("%s-%d-funcport", - cpu->name(), tid), - process->pTable, false); - mem_port = memobj->getPort("functional"); - mem_port->setPeer(port); - port->setPeer(mem_port); - regs.clear(); tc = new ProxyThreadContext(this); } @@ -127,9 +118,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, SimpleThread::SimpleThread() #if FULL_SYSTEM - : ThreadState(-1, -1) + : ThreadState(NULL, -1, -1) #else - : ThreadState(-1, -1, NULL, -1, NULL) + : ThreadState(NULL, -1, -1, NULL, -1) #endif { tc = new ProxyThreadContext(this); @@ -332,6 +323,25 @@ SimpleThread::delVirtPort(VirtualPort *vp) } } +#else +TranslatingPort * +SimpleThread::getMemPort() +{ + if (port != NULL) + return port; + + /* Use this port to for syscall emulation writes to memory. */ + Port *dcache_port; + port = new TranslatingPort(csprintf("%s-%d-funcport", + cpu->name(), tid), + process->pTable, false); + dcache_port = cpu->getPort("dcache_port"); + assert(dcache_port != NULL); + dcache_port = dcache_port->getPeer(); +// mem_port->setPeer(port); + port->setPeer(dcache_port); + return port; +} #endif diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fe22e6c43..f002cbdce 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -117,8 +117,7 @@ class SimpleThread : public ThreadState AlphaITB *_itb, AlphaDTB *_dtb, bool use_kernel_stats = true); #else - SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid, - MemObject *memobj); + SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); #endif SimpleThread(); @@ -174,6 +173,9 @@ class SimpleThread : public ThreadState bool simPalCheck(int palFunc); #else + // Override this function. + TranslatingPort *getMemPort(); + Fault translateInstReq(RequestPtr &req) { return process->pTable->translate(req); diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index c644ae8d7..677ba6592 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -29,8 +29,11 @@ */ #include "base/output.hh" +#include "cpu/base.hh" #include "cpu/profile.hh" #include "cpu/thread_state.hh" +#include "mem/port.hh" +#include "mem/translating_port.hh" #include "sim/serialize.hh" #if FULL_SYSTEM @@ -39,15 +42,16 @@ #endif #if FULL_SYSTEM -ThreadState::ThreadState(int _cpuId, int _tid) - : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), +ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid) + : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL), + physPort(NULL), virtPort(NULL), microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) #else -ThreadState::ThreadState(int _cpuId, int _tid, Process *_process, - short _asid, MemObject *mem) - : cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), - process(_process), asid(_asid), +ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, + short _asid) + : baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0), + port(NULL), process(_process), asid(_asid), microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0) #endif { @@ -108,4 +112,31 @@ ThreadState::profileSample() profile->sample(profileNode, profilePC); } +#else +TranslatingPort * +ThreadState::getMemPort() +{ + if (port != NULL) + return port; + + /* Use this port to for syscall emulation writes to memory. */ + Port *dcache_port, *func_mem_port; + port = new TranslatingPort(csprintf("%s-%d-funcport", + baseCpu->name(), tid), + process->pTable, false); + + dcache_port = baseCpu->getPort("dcache_port"); + assert(dcache_port != NULL); + + MemObject *mem_object = dcache_port->getPeer()->getOwner(); + assert(mem_object != NULL); + + func_mem_port = mem_object->getPort("functional"); + assert(func_mem_port != NULL); + + func_mem_port->setPeer(port); + port->setPeer(func_mem_port); + + return port; +} #endif diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 60353760c..14673aabb 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -37,7 +37,6 @@ #if !FULL_SYSTEM #include "mem/mem_object.hh" -#include "mem/translating_port.hh" #include "sim/process.hh" #endif @@ -50,7 +49,9 @@ namespace Kernel { }; #endif +class BaseCPU; class Checkpoint; +class TranslatingPort; /** * Struct for holding general thread state that is needed across CPU @@ -62,10 +63,10 @@ struct ThreadState { typedef ThreadContext::Status Status; #if FULL_SYSTEM - ThreadState(int _cpuId, int _tid); + ThreadState(BaseCPU *cpu, int _cpuId, int _tid); #else - ThreadState(int _cpuId, int _tid, Process *_process, - short _asid, MemObject *mem); + ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, + short _asid); #endif void serialize(std::ostream &os); @@ -105,7 +106,7 @@ struct ThreadState { #else Process *getProcessPtr() { return process; } - TranslatingPort *getMemPort() { return port; } + TranslatingPort *getMemPort(); void setMemPort(TranslatingPort *_port) { port = _port; } @@ -153,6 +154,9 @@ struct ThreadState { protected: ThreadContext::Status _status; + // Pointer to the base CPU. + BaseCPU *baseCpu; + // ID of this context w.r.t. the System or Process object to which // it belongs. For full-system mode, this is the system CPU ID. int cpuId; -- cgit v1.2.3 From 2b11b4735761cdb5fcf32bbe0fb1cd96b7498db0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 1 Nov 2006 16:44:45 -0500 Subject: Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675 --- src/cpu/checker/cpu.hh | 23 +++++++++++++---------- src/cpu/checker/thread_context.hh | 16 ++++++++-------- src/cpu/exec_context.hh | 6 +++--- src/cpu/o3/alpha/cpu.hh | 16 +++++++++++----- src/cpu/o3/alpha/cpu_builder.cc | 4 ++-- src/cpu/o3/alpha/cpu_impl.hh | 13 ++++++------- src/cpu/o3/alpha/dyn_inst.hh | 9 ++++----- src/cpu/o3/alpha/params.hh | 11 +++++++---- src/cpu/o3/alpha/thread_context.hh | 4 ++-- src/cpu/o3/checker_builder.cc | 4 ++-- src/cpu/o3/mips/cpu.hh | 7 +++---- src/cpu/o3/mips/cpu_impl.hh | 13 ++++++------- src/cpu/o3/mips/dyn_inst.hh | 11 +++++------ src/cpu/o3/regfile.hh | 14 ++++++-------- src/cpu/o3/thread_context.hh | 8 ++++---- src/cpu/o3/thread_context_impl.hh | 13 ++++--------- src/cpu/ozone/checker_builder.cc | 4 ++-- src/cpu/ozone/cpu.hh | 17 ++++++++++------- src/cpu/ozone/cpu_builder.cc | 4 ++-- src/cpu/ozone/cpu_impl.hh | 18 ++++++------------ src/cpu/ozone/dyn_inst.hh | 6 +++--- src/cpu/ozone/dyn_inst_impl.hh | 12 ++++++------ src/cpu/ozone/simple_cpu_builder.cc | 4 ++-- src/cpu/ozone/simple_params.hh | 9 ++++++--- src/cpu/ozone/thread_state.hh | 10 +++++----- src/cpu/simple/base.hh | 8 ++++---- src/cpu/simple_thread.hh | 8 ++++---- src/cpu/thread_context.hh | 14 +++++++------- 28 files changed, 143 insertions(+), 143 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 7c01bdc39..0df0147ae 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -47,9 +47,12 @@ // forward declarations #if FULL_SYSTEM +namespace TheISA +{ + class ITB; + class DTB; +} class Processor; -class AlphaITB; -class AlphaDTB; class PhysicalMemory; class RemoteGDB; @@ -96,8 +99,8 @@ class CheckerCPU : public BaseCPU struct Params : public BaseCPU::Params { #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #else Process *process; #endif @@ -140,8 +143,8 @@ class CheckerCPU : public BaseCPU ThreadContext *tc; - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; #if FULL_SYSTEM Addr dbg_vtophys(Addr addr); @@ -301,19 +304,19 @@ class CheckerCPU : public BaseCPU return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return thread->readMiscRegWithEffect(misc_reg, fault); + return thread->readMiscRegWithEffect(misc_reg); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { result.integer = val; miscRegIdxs.push(misc_reg); return thread->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { miscRegIdxs.push(misc_reg); return thread->setMiscRegWithEffect(misc_reg, val); diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index b2806d40b..cd399dd22 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -87,9 +87,9 @@ class CheckerThreadContext : public ThreadContext PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); } - AlphaITB *getITBPtr() { return actualTC->getITBPtr(); } + TheISA::ITB *getITBPtr() { return actualTC->getITBPtr(); } - AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); } + TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } @@ -248,19 +248,19 @@ class CheckerThreadContext : public ThreadContext MiscReg readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return actualTC->readMiscRegWithEffect(misc_reg, fault); } + MiscReg readMiscRegWithEffect(int misc_reg) + { return actualTC->readMiscRegWithEffect(misc_reg); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { checkerTC->setMiscReg(misc_reg, val); - return actualTC->setMiscReg(misc_reg, val); + actualTC->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { checkerTC->setMiscRegWithEffect(misc_reg, val); - return actualTC->setMiscRegWithEffect(misc_reg, val); + actualTC->setMiscRegWithEffect(misc_reg, val); } unsigned readStCondFailures() diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index e28b33193..13f70fa79 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -101,14 +101,14 @@ class ExecContext { /** Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); /** Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); /** Records the effective address of the instruction. Only valid * for memory ops. */ diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 474fce02a..01749a2a2 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -37,6 +37,12 @@ #include "cpu/o3/cpu.hh" #include "sim/byteswap.hh" +namespace TheISA +{ + class ITB; + class DTB; +} + class EndQuiesceEvent; namespace Kernel { class Statistics; @@ -73,9 +79,9 @@ class AlphaO3CPU : public FullO3CPU #if FULL_SYSTEM /** ITB pointer. */ - AlphaITB *itb; + AlphaISA::ITB *itb; /** DTB pointer. */ - AlphaDTB *dtb; + AlphaISA::DTB *dtb; #endif /** Registers statistics. */ @@ -126,15 +132,15 @@ class AlphaO3CPU : public FullO3CPU /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid); + MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given * thread. The source of the squash is an external update of diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index ff123a6f7..a00dd5005 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -54,8 +54,8 @@ Param activity; #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; Param profile; #else SimObjectVectorParam workload; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index a57c5d9ed..7f10e43c2 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -198,25 +198,24 @@ AlphaO3CPU::readMiscReg(int misc_reg, unsigned tid) template TheISA::MiscReg -AlphaO3CPU::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +AlphaO3CPU::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template -Fault +void AlphaO3CPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template -Fault +void AlphaO3CPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 31a6f7753..e711de510 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -102,14 +102,13 @@ class AlphaDynInst : public BaseDynInst /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); @@ -118,7 +117,7 @@ class AlphaDynInst : public BaseDynInst /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh index c618cee08..b6b84b2a1 100644 --- a/src/cpu/o3/alpha/params.hh +++ b/src/cpu/o3/alpha/params.hh @@ -35,8 +35,11 @@ #include "cpu/o3/params.hh" //Forward declarations -class AlphaDTB; -class AlphaITB; +namespace AlphaISA +{ + class DTB; + class ITB; +} class MemObject; class Process; class System; @@ -52,8 +55,8 @@ class AlphaSimpleParams : public O3Params public: #if FULL_SYSTEM - AlphaITB *itb; - AlphaDTB *dtb; + AlphaISA::ITB *itb; + AlphaISA::DTB *dtb; #endif }; diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index 70a09940f..f0cecee35 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -37,10 +37,10 @@ class AlphaTC : public O3ThreadContext public: #if FULL_SYSTEM /** Returns a pointer to the ITB. */ - virtual AlphaITB *getITBPtr() { return this->cpu->itb; } + virtual AlphaISA::ITB *getITBPtr() { return this->cpu->itb; } /** Returns a pointer to the DTB. */ - virtual AlphaDTB *getDTBPtr() { return this->cpu->dtb; } + virtual AlphaISA::DTB *getDTBPtr() { return this->cpu->dtb; } /** Returns pointer to the quiesce event. */ virtual EndQuiesceEvent *getQuiesceEvent() diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 02c817499..8b028e3a0 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -67,8 +67,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param progress_interval; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; SimObjectParam system; Param cpu_id; Param profile; diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh index bf04b9f69..7e6268cdf 100755 --- a/src/cpu/o3/mips/cpu.hh +++ b/src/cpu/o3/mips/cpu.hh @@ -92,16 +92,15 @@ class MipsO3CPU : public FullO3CPU /** Reads a misc. register, including any side effects the read * might have as defined by the architecture. */ - TheISA::MiscReg readMiscRegWithEffect(int misc_reg, - Fault &fault, unsigned tid); + TheISA::MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid); /** Sets a miscellaneous register. */ - Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Sets a misc. register, including any side effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, + void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); /** Initiates a squash of all in-flight instructions for a given diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh index e08741626..5633acee1 100644 --- a/src/cpu/o3/mips/cpu_impl.hh +++ b/src/cpu/o3/mips/cpu_impl.hh @@ -156,25 +156,24 @@ MipsO3CPU::readMiscReg(int misc_reg, unsigned tid) template MiscReg -MipsO3CPU::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +MipsO3CPU::readMiscRegWithEffect(int misc_reg, unsigned tid) { - return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); + return this->regFile.readMiscRegWithEffect(misc_reg, tid); } template -Fault +void MipsO3CPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscReg(misc_reg, val, tid); + this->regFile.setMiscReg(misc_reg, val, tid); } template -Fault +void MipsO3CPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid) { - return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); + this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index aa30bfa1e..9e95b2bfb 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -103,23 +103,22 @@ class MipsDynInst : public BaseDynInst /** Reads a misc. register, including any side-effects the read * might have as defined by the architecture. */ - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return this->cpu->readMiscRegWithEffect(misc_reg, fault, - this->threadNumber); + return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber); } /** Sets a misc. register. */ - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { this->instResult.integer = val; - return this->cpu->setMiscReg(misc_reg, val, this->threadNumber); + this->cpu->setMiscReg(misc_reg, val, this->threadNumber); } /** Sets a misc. register, including any side-effects the write * might have as defined by the architecture. */ - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return this->cpu->setMiscRegWithEffect(misc_reg, val, this->threadNumber); diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 10f6db390..29ee19e49 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -37,7 +37,6 @@ #include "base/trace.hh" #include "config/full_system.hh" #include "cpu/o3/comm.hh" -#include "sim/faults.hh" #if FULL_SYSTEM #include "kern/kernel_stats.hh" @@ -232,22 +231,21 @@ class PhysRegFile return miscRegs[thread_id].readReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned thread_id) + MiscReg readMiscRegWithEffect(int misc_reg, unsigned thread_id) { - return miscRegs[thread_id].readRegWithEffect(misc_reg, fault, + return miscRegs[thread_id].readRegWithEffect(misc_reg, cpu->tcBase(thread_id)); } - Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) + void setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id) { - return miscRegs[thread_id].setReg(misc_reg, val); + miscRegs[thread_id].setReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, + void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned thread_id) { - return miscRegs[thread_id].setRegWithEffect(misc_reg, val, + miscRegs[thread_id].setRegWithEffect(misc_reg, val, cpu->tcBase(thread_id)); } diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 9ca02b9f3..4556c5e22 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -201,15 +201,15 @@ class O3ThreadContext : public ThreadContext /** Reads a misc. register, including any side-effects the * read might have as defined by the architecture. */ - virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return cpu->readMiscRegWithEffect(misc_reg, fault, thread->readTid()); } + virtual MiscReg readMiscRegWithEffect(int misc_reg) + { return cpu->readMiscRegWithEffect(misc_reg, thread->readTid()); } /** Sets a misc. register. */ - virtual Fault setMiscReg(int misc_reg, const MiscReg &val); + virtual void setMiscReg(int misc_reg, const MiscReg &val); /** Sets a misc. register, including any side-effects the * write might have as defined by the architecture. */ - virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val); /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 2bc194d53..81750ada7 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -439,33 +439,28 @@ O3ThreadContext::setNextPC(uint64_t val) } template -Fault +void O3ThreadContext::setMiscReg(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); + cpu->setMiscReg(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } template -Fault +void O3ThreadContext::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, - thread->readTid()); + cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); // Squash if we're not already in a state update mode. if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->readTid()); } - - return ret_fault; } #if !FULL_SYSTEM diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index b4c4686b7..9ad1e639f 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -68,8 +68,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param progress_interval; #if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; + SimObjectParam itb; + SimObjectParam dtb; SimObjectParam system; Param cpu_id; Param profile; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index bd46b198b..14c32620b 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -51,8 +51,11 @@ #if FULL_SYSTEM #include "arch/alpha/tlb.hh" -class AlphaITB; -class AlphaDTB; +namespace TheISA +{ + class ITB; + class DTB; +} class PhysicalMemory; class MemoryController; @@ -120,9 +123,9 @@ class OzoneCPU : public BaseCPU PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } - AlphaITB *getITBPtr() { return cpu->itb; } + TheISA::ITB *getITBPtr() { return cpu->itb; } - AlphaDTB * getDTBPtr() { return cpu->dtb; } + TheISA::DTB * getDTBPtr() { return cpu->dtb; } Kernel::Statistics *getKernelStats() { return thread->getKernelStats(); } @@ -224,11 +227,11 @@ class OzoneCPU : public BaseCPU // ISA stuff: MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); unsigned readStCondFailures() { return thread->storeCondFailures; } diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index 730158258..8a572ba38 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -61,8 +61,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU) #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; Param profile; #else SimObjectVectorParam workload; diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index bf547bf94..b34b061d9 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -1156,37 +1156,31 @@ OzoneCPU::OzoneTC::readMiscReg(int misc_reg) template TheISA::MiscReg -OzoneCPU::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneCPU::OzoneTC::readMiscRegWithEffect(int misc_reg) { - return thread->miscRegFile.readRegWithEffect(misc_reg, - fault, this); + return thread->miscRegFile.readRegWithEffect(misc_reg, this); } template -Fault +void OzoneCPU::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - Fault ret_fault = thread->miscRegFile.setReg(misc_reg, val); + thread->miscRegFile.setReg(misc_reg, val); if (!thread->inSyscall) { cpu->squashFromTC(); } - - return ret_fault; } template -Fault +void OzoneCPU::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { // Needs to setup a squash event unless we're in syscall mode - Fault ret_fault = thread->miscRegFile.setRegWithEffect(misc_reg, val, - this); + thread->miscRegFile.setRegWithEffect(misc_reg, val, this); if (!thread->inSyscall) { cpu->squashFromTC(); } - - return ret_fault; } diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index d3871568a..532317b08 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -230,11 +230,11 @@ class OzoneDynInst : public BaseDynInst // ISA stuff MiscReg readMiscReg(int misc_reg); - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault); + MiscReg readMiscRegWithEffect(int misc_reg); - Fault setMiscReg(int misc_reg, const MiscReg &val); + void setMiscReg(int misc_reg, const MiscReg &val); - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val); + void setMiscRegWithEffect(int misc_reg, const MiscReg &val); #if FULL_SYSTEM Fault hwrei(); diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index d86f2dc8b..68736ae61 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -223,24 +223,24 @@ OzoneDynInst::readMiscReg(int misc_reg) template TheISA::MiscReg -OzoneDynInst::readMiscRegWithEffect(int misc_reg, Fault &fault) +OzoneDynInst::readMiscRegWithEffect(int misc_reg) { - return this->thread->readMiscRegWithEffect(misc_reg, fault); + return this->thread->readMiscRegWithEffect(misc_reg); } template -Fault +void OzoneDynInst::setMiscReg(int misc_reg, const MiscReg &val) { this->setIntResult(val); - return this->thread->setMiscReg(misc_reg, val); + this->thread->setMiscReg(misc_reg, val); } template -Fault +void OzoneDynInst::setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return this->thread->setMiscRegWithEffect(misc_reg, val); + this->thread->setMiscRegWithEffect(misc_reg, val); } #if FULL_SYSTEM diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc index baaf7c708..e7214d2ba 100644 --- a/src/cpu/ozone/simple_cpu_builder.cc +++ b/src/cpu/ozone/simple_cpu_builder.cc @@ -64,8 +64,8 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU) #if FULL_SYSTEM SimObjectParam system; Param cpu_id; -SimObjectParam itb; -SimObjectParam dtb; +SimObjectParam itb; +SimObjectParam dtb; #else SimObjectVectorParam workload; //SimObjectParam page_table; diff --git a/src/cpu/ozone/simple_params.hh b/src/cpu/ozone/simple_params.hh index 3f63d2e1d..3473b088c 100644 --- a/src/cpu/ozone/simple_params.hh +++ b/src/cpu/ozone/simple_params.hh @@ -34,8 +34,11 @@ #include "cpu/ozone/cpu.hh" //Forward declarations -class AlphaDTB; -class AlphaITB; +namespace TheISA +{ + class DTB; + class ITB; +} class FUPool; class MemObject; class PageTable; @@ -53,7 +56,7 @@ class SimpleParams : public BaseCPU::Params public: #if FULL_SYSTEM - AlphaITB *itb; AlphaDTB *dtb; + TheISA::ITB *itb; TheISA::DTB *dtb; #else std::vector workload; #endif // FULL_SYSTEM diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index 985e09b52..ec51251b7 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -120,19 +120,19 @@ struct OzoneThreadState : public ThreadState { return miscRegFile.readReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { return miscRegFile.readRegWithEffect(misc_reg, fault, tc); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { - return miscRegFile.setReg(misc_reg, val); + miscRegFile.setReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { - return miscRegFile.setRegWithEffect(misc_reg, val, tc); + miscRegFile.setRegWithEffect(misc_reg, val, tc); } uint64_t readPC() diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 1d208b8df..5c8d569bb 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -288,17 +288,17 @@ class BaseSimpleCPU : public BaseCPU return thread->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return thread->readMiscRegWithEffect(misc_reg, fault); + return thread->readMiscRegWithEffect(misc_reg); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { return thread->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return thread->setMiscRegWithEffect(misc_reg, val); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index d005b2914..20f7f0d1c 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -420,17 +420,17 @@ class SimpleThread : public ThreadState return regs.readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) + MiscReg readMiscRegWithEffect(int misc_reg) { - return regs.readMiscRegWithEffect(misc_reg, fault, tc); + return regs.readMiscRegWithEffect(misc_reg, tc); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { return regs.setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return regs.setMiscRegWithEffect(misc_reg, val, tc); } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 448d67d02..dfc6fbc2a 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -224,11 +224,11 @@ class ThreadContext virtual MiscReg readMiscReg(int misc_reg) = 0; - virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0; + virtual MiscReg readMiscRegWithEffect(int misc_reg) = 0; - virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; - virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; + virtual void setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0; // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. @@ -410,13 +410,13 @@ class ProxyThreadContext : public ThreadContext MiscReg readMiscReg(int misc_reg) { return actualTC->readMiscReg(misc_reg); } - MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) - { return actualTC->readMiscRegWithEffect(misc_reg, fault); } + MiscReg readMiscRegWithEffect(int misc_reg) + { return actualTC->readMiscRegWithEffect(misc_reg); } - Fault setMiscReg(int misc_reg, const MiscReg &val) + void setMiscReg(int misc_reg, const MiscReg &val) { return actualTC->setMiscReg(misc_reg, val); } - Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) + void setMiscRegWithEffect(int misc_reg, const MiscReg &val) { return actualTC->setMiscRegWithEffect(misc_reg, val); } unsigned readStCondFailures() -- cgit v1.2.3 From ccaf80cc46fb86639ab5ee166baca08277f5450f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 2 Nov 2006 13:11:38 -0500 Subject: Use ISA specific makeExtMI. src/arch/alpha/utility.hh: For now makeExtMI will be specific to the ISA. --HG-- extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496 --- src/cpu/checker/cpu_impl.hh | 5 +++++ src/cpu/o3/fetch_impl.hh | 6 +++++- src/cpu/ozone/front_end_impl.hh | 4 ++++ src/cpu/simple/base.cc | 4 ++++ 4 files changed, 18 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 36c7349e6..56e13dd1e 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -199,8 +199,13 @@ Checker::verify(DynInstPtr &completed_inst) // Checks both the machine instruction and the PC. validateInst(inst); +#if THE_ISA == ALPHA_ISA + curStaticInst = StaticInst::decode(makeExtMI(machInst, + thread->readPC())); +#elif THE_ISA == SPARC_ISA curStaticInst = StaticInst::decode(makeExtMI(machInst, thread->getTC())); +#endif #if FULL_SYSTEM thread->setInst(machInst); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 2b152e376..31f3b96d6 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1117,7 +1117,11 @@ DefaultFetch::fetch(bool &status_change) inst = TheISA::gtoh(*reinterpret_cast (&cacheData[tid][offset])); - ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid)); +#if THE_ISA == ALPHA_ISA + ext_inst = TheISA::makeExtMI(inst, fetch_PC); +#elif THE_ISA == SPARC_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(ext_inst, fetch_PC, diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 63cf0a952..6d02c58cb 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -882,7 +882,11 @@ FrontEnd::getInstFromCacheline() // Get the instruction from the array of the cache line. inst = htog(*reinterpret_cast(&cacheData[offset])); +#if THE_ISA == ALPHA_ISA + ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC); +#elif THE_ISA == SPARC_ISA ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc); +#endif // Create a new DynInst from the instruction fetched. DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst), diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 47b3b938f..6a2c0bbe9 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -398,7 +398,11 @@ BaseSimpleCPU::preExecute() inst = gtoh(inst); //If we're not in the middle of a macro instruction if (!curMacroStaticInst) { +#if THE_ISA == ALPHA_ISA + StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC())); +#elif THE_ISA == SPARC_ISA StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); +#endif if (instPtr->isMacroOp()) { curMacroStaticInst = instPtr; curStaticInst = curMacroStaticInst-> -- cgit v1.2.3 From 64f8cd12c6a613205196bbe9dbc0fab98c4ca735 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 2 Nov 2006 13:12:36 -0500 Subject: Remove function that should have been deleted. src/cpu/simple_thread.cc: This function should have been deleted from an earlier push. src/cpu/simple_thread.hh: Delete this function; it's now in thread_state.hh/.cc. --HG-- extra : convert_revision : f78dcf9c2b388418030d48d0ea4911c8b8b1f5ff --- src/cpu/simple_thread.cc | 20 -------------------- src/cpu/simple_thread.hh | 2 -- 2 files changed, 22 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index c89a13eef..28d8bdf62 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -323,25 +323,5 @@ SimpleThread::delVirtPort(VirtualPort *vp) } } -#else -TranslatingPort * -SimpleThread::getMemPort() -{ - if (port != NULL) - return port; - - /* Use this port to for syscall emulation writes to memory. */ - Port *dcache_port; - port = new TranslatingPort(csprintf("%s-%d-funcport", - cpu->name(), tid), - process->pTable, false); - dcache_port = cpu->getPort("dcache_port"); - assert(dcache_port != NULL); - dcache_port = dcache_port->getPeer(); -// mem_port->setPeer(port); - port->setPeer(dcache_port); - return port; -} - #endif diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index f002cbdce..20001063a 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -173,8 +173,6 @@ class SimpleThread : public ThreadState bool simPalCheck(int palFunc); #else - // Override this function. - TranslatingPort *getMemPort(); Fault translateInstReq(RequestPtr &req) { -- cgit v1.2.3 From dd5e2cd959e61b8af094137f337e999048317ec3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 2 Nov 2006 14:58:31 -0500 Subject: More proper handling of the ports. src/cpu/simple_thread.cc: Fix up port handling to share code. src/cpu/thread_state.cc: Separate code off into a function. src/cpu/thread_state.hh: Make a separate function that will get the CPU's memory's functional port. --HG-- extra : convert_revision : 96a9bb3c5e4b9ba5511678c0fd17f0017c8cd312 --- src/cpu/simple_thread.cc | 10 ++++++---- src/cpu/thread_state.cc | 31 +++++++++++++++++++++++++------ src/cpu/thread_state.hh | 9 +++++++++ 3 files changed, 40 insertions(+), 10 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 28d8bdf62..f5fa68529 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -129,6 +129,10 @@ SimpleThread::SimpleThread() SimpleThread::~SimpleThread() { +#if FULL_SYSTEM + delete physPort; + delete virtPort; +#endif delete tc; } @@ -304,11 +308,9 @@ SimpleThread::getVirtPort(ThreadContext *src_tc) if (!src_tc) return virtPort; - VirtualPort *vp; - Port *mem_port; + VirtualPort *vp = new VirtualPort("tc-vport", src_tc); + Port *mem_port = getMemFuncPort(); - vp = new VirtualPort("tc-vport", src_tc); - mem_port = system->physmem->getPort("functional"); mem_port->setPeer(vp); vp->setPeer(mem_port); return vp; diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index f81b78147..a6fff5fc3 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -59,6 +59,16 @@ ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process, numLoad = 0; } +ThreadState::~ThreadState() +{ +#if !FULL_SYSTEM + if (port) { + delete port->getPeer(); + delete port; + } +#endif +} + void ThreadState::serialize(std::ostream &os) { @@ -124,11 +134,24 @@ ThreadState::getMemPort() return port; /* Use this port to for syscall emulation writes to memory. */ - Port *dcache_port, *func_mem_port; port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid), process->pTable, false); + Port *func_port = getMemFuncPort(); + + func_port->setPeer(port); + port->setPeer(func_port); + + return port; +} +#endif + +Port * +ThreadState::getMemFuncPort() +{ + Port *dcache_port, *func_mem_port; + dcache_port = baseCpu->getPort("dcache_port"); assert(dcache_port != NULL); @@ -138,9 +161,5 @@ ThreadState::getMemPort() func_mem_port = mem_object->getPort("functional"); assert(func_mem_port != NULL); - func_mem_port->setPeer(port); - port->setPeer(func_mem_port); - - return port; + return func_mem_port; } -#endif diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 14673aabb..862d671f2 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -51,6 +51,7 @@ namespace Kernel { class BaseCPU; class Checkpoint; +class Port; class TranslatingPort; /** @@ -69,6 +70,8 @@ struct ThreadState { short _asid); #endif + ~ThreadState(); + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); @@ -136,6 +139,12 @@ struct ThreadState { /** Sets the status of this thread. */ void setStatus(Status new_status) { _status = new_status; } + protected: + /** Gets a functional port from the memory object that's connected + * to the CPU. */ + Port *getMemFuncPort(); + + public: /** Number of instructions committed. */ Counter numInst; /** Stat for number instructions committed. */ -- cgit v1.2.3 From c8fc116c7636893517254f785707eba1726d3265 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 02:25:39 -0500 Subject: Add a new file which describes an ISA's interrupt handling mechanism. It records when interrupts are requested, and returns an interrupt to execute if the --HG-- extra : convert_revision : c535000a6a170caefd441687b60f940513d29739 --- src/cpu/base.cc | 43 ++++++--------------------------------- src/cpu/base.hh | 18 +++++++++-------- src/cpu/o3/alpha/cpu_impl.hh | 48 +++----------------------------------------- src/cpu/simple/base.cc | 37 +++------------------------------- 4 files changed, 22 insertions(+), 124 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index ea4b03bf2..66c5d3e11 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -168,11 +168,6 @@ BaseCPU::BaseCPU(Params *p) p->max_loads_all_threads, *counter); } -#if FULL_SYSTEM - memset(interrupts, 0, sizeof(interrupts)); - intstatus = 0; -#endif - functionTracingEnabled = false; if (p->functionTrace) { functionTraceStream = simout.find(csprintf("ftrace.%s", name())); @@ -314,9 +309,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) } #if FULL_SYSTEM - for (int i = 0; i < TheISA::NumInterruptLevels; ++i) - interrupts[i] = oldCPU->interrupts[i]; - intstatus = oldCPU->intstatus; + interrupts = oldCPU->interrupts; checkInterrupts = oldCPU->checkInterrupts; for (int i = 0; i < threadContexts.size(); ++i) @@ -348,57 +341,33 @@ BaseCPU::ProfileEvent::process() void BaseCPU::post_interrupt(int int_num, int index) { - DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); - - if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) - panic("int_num out of bounds\n"); - - if (index < 0 || index >= sizeof(uint64_t) * 8) - panic("int_num out of bounds\n"); - checkInterrupts = true; - interrupts[int_num] |= 1 << index; - intstatus |= (ULL(1) << int_num); + interrupts.post(int_num, index); } void BaseCPU::clear_interrupt(int int_num, int index) { - DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); - - if (int_num < 0 || int_num >= TheISA::NumInterruptLevels) - panic("int_num out of bounds\n"); - - if (index < 0 || index >= sizeof(uint64_t) * 8) - panic("int_num out of bounds\n"); - - interrupts[int_num] &= ~(1 << index); - if (interrupts[int_num] == 0) - intstatus &= ~(ULL(1) << int_num); + interrupts.clear(int_num, index); } void BaseCPU::clear_interrupts() { - DPRINTF(Interrupt, "Interrupts all cleared\n"); - - memset(interrupts, 0, sizeof(interrupts)); - intstatus = 0; + interrupts.clear_all(); } void BaseCPU::serialize(std::ostream &os) { - SERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); - SERIALIZE_SCALAR(intstatus); + interrupts.serialize(os); } void BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) { - UNSERIALIZE_ARRAY(interrupts, TheISA::NumInterruptLevels); - UNSERIALIZE_SCALAR(intstatus); + interrupts.unserialize(cp, section); } #endif // FULL_SYSTEM diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 75e0d86af..207473d80 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -40,6 +40,10 @@ #include "mem/mem_object.hh" #include "arch/isa_traits.hh" +#if FULL_SYSTEM +#include "arch/interrupts.hh" +#endif + class BranchPred; class CheckerCPU; class ThreadContext; @@ -75,8 +79,9 @@ class BaseCPU : public MemObject #if FULL_SYSTEM protected: - uint64_t interrupts[TheISA::NumInterruptLevels]; - uint64_t intstatus; +// uint64_t interrupts[TheISA::NumInterruptLevels]; +// uint64_t intstatus; + TheISA::Interrupts interrupts; public: virtual void post_interrupt(int int_num, int index); @@ -85,14 +90,11 @@ class BaseCPU : public MemObject bool checkInterrupts; bool check_interrupt(int int_num) const { - if (int_num > TheISA::NumInterruptLevels) - panic("int_num out of bounds\n"); - - return interrupts[int_num] != 0; + return interrupts.check_interrupt(int_num); } - bool check_interrupts() const { return intstatus != 0; } - uint64_t intr_status() const { return intstatus; } + bool check_interrupts() const { return interrupts.check_interrupts(); } + //uint64_t intr_status() const { return interrupts.intr_status(); } class ProfileEvent : public Event { diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index f5c2170ce..170a53c23 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -270,7 +270,6 @@ template void AlphaO3CPU::processInterrupts() { - using namespace TheISA; // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 // is the one that handles the interrupts. @@ -279,52 +278,11 @@ AlphaO3CPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - int ipl = 0; - int summary = 0; - this->checkInterrupts = false; + Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (this->readMiscReg(IPR_ASTRR, 0)) - panic("asynchronous traps not implemented\n"); - - if (this->readMiscReg(IPR_SIRR, 0)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (this->readMiscReg(IPR_SIRR, 0) & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = this->intr_status(); - - if (interrupts) { - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of the 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - } - - if (ipl && ipl > this->readMiscReg(IPR_IPLR, 0)) { - this->setMiscReg(IPR_ISR, summary, 0); - this->setMiscReg(IPR_INTID, ipl, 0); - // Checker needs to know these two registers were updated. -#if USE_CHECKER - if (this->checker) { - this->checker->threadBase()->setMiscReg(IPR_ISR, summary); - this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); - } -#endif - this->trap(Fault(new InterruptFault), 0); - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - this->readMiscReg(IPR_IPLR, 0), ipl, summary); - } + if (interrupt != NoFault) + this->trap(interrupt, 0); } #endif // FULL_SYSTEM diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 6a2c0bbe9..0c7b5eafe 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -312,42 +312,11 @@ BaseSimpleCPU::checkForInterrupts() { #if FULL_SYSTEM if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { - int ipl = 0; - int summary = 0; checkInterrupts = false; + Fault interrupt = interrupts.getInterrupt(tc); - if (thread->readMiscReg(IPR_SIRR)) { - for (int i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - uint64_t interrupts = thread->cpu->intr_status(); - for (int i = INTLEVEL_EXTERNAL_MIN; - i < INTLEVEL_EXTERNAL_MAX; i++) { - if (interrupts & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - - if (thread->readMiscReg(IPR_ASTRR)) - panic("asynchronous traps not implemented\n"); - - if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) { - thread->setMiscReg(IPR_ISR, summary); - thread->setMiscReg(IPR_INTID, ipl); - - Fault(new InterruptFault)->invoke(tc); - - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - thread->readMiscReg(IPR_IPLR), ipl, summary); + if (interrupt != NoFault) { + interrupt->invoke(tc); } } #endif -- cgit v1.2.3 From 118b9dc1f9e84a12ea26743f6cec1eac5b4ab13a Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 04:25:33 -0500 Subject: Got rid of "inPalMode". Some places are still effectively checking if they are in PAL mode, however. --HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b --- src/cpu/base.hh | 8 ++------ src/cpu/checker/cpu.hh | 1 - src/cpu/checker/thread_context.hh | 3 --- src/cpu/o3/alpha/cpu.hh | 3 --- src/cpu/o3/alpha/cpu_impl.hh | 5 +++-- src/cpu/o3/alpha/dyn_inst.hh | 2 -- src/cpu/o3/alpha/dyn_inst_impl.hh | 9 +-------- src/cpu/o3/alpha/thread_context.hh | 5 ----- src/cpu/o3/commit_impl.hh | 3 +-- src/cpu/o3/fetch_impl.hh | 13 ++++--------- src/cpu/ozone/cpu.hh | 6 ------ src/cpu/ozone/dyn_inst.hh | 1 - src/cpu/ozone/dyn_inst_impl.hh | 9 +-------- src/cpu/ozone/front_end_impl.hh | 9 ++------- src/cpu/ozone/inorder_back_end_impl.hh | 6 +++--- src/cpu/ozone/lw_back_end_impl.hh | 3 +-- src/cpu/simple/base.cc | 8 ++++++-- src/cpu/simple/base.hh | 1 - src/cpu/simple_thread.hh | 4 ---- src/cpu/thread_context.hh | 7 ------- 20 files changed, 24 insertions(+), 82 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 207473d80..79d22c992 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -89,12 +89,8 @@ class BaseCPU : public MemObject virtual void clear_interrupts(); bool checkInterrupts; - bool check_interrupt(int int_num) const { - return interrupts.check_interrupt(int_num); - } - - bool check_interrupts() const { return interrupts.check_interrupts(); } - //uint64_t intr_status() const { return interrupts.intr_status(); } + bool check_interrupts(ThreadContext * tc) const + { return interrupts.check_interrupts(tc); } class ProfileEvent : public Event { diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 454f3892b..9be54529f 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -327,7 +327,6 @@ class CheckerCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } #else diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index cd399dd22..b46031167 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -271,9 +271,6 @@ class CheckerThreadContext : public ThreadContext checkerTC->setStCondFailures(sc_failures); actualTC->setStCondFailures(sc_failures); } -#if FULL_SYSTEM - bool inPalMode() { return actualTC->inPalMode(); } -#endif // @todo: Fix this! bool misspeculating() { return actualTC->misspeculating(); } diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh index 01749a2a2..b62550062 100644 --- a/src/cpu/o3/alpha/cpu.hh +++ b/src/cpu/o3/alpha/cpu.hh @@ -153,9 +153,6 @@ class AlphaO3CPU : public FullO3CPU void post_interrupt(int int_num, int index); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); - /** Returns if a specific PC is a PAL mode PC. */ - bool inPalMode(uint64_t PC) - { return AlphaISA::PcPAL(PC); } bool simPalCheck(int palFunc, unsigned tid); diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 170a53c23..750ccc912 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -278,11 +278,12 @@ AlphaO3CPU::processInterrupts() // Check if there are any outstanding interrupts //Handle the interrupts - this->checkInterrupts = false; Fault interrupt = this->interrupts.getInterrupt(this->tcBase(0)); - if (interrupt != NoFault) + if (interrupt != NoFault) { + this->checkInterrupts = false; this->trap(interrupt, 0); + } } #endif // FULL_SYSTEM diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index e711de510..31df8ff78 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -126,8 +126,6 @@ class AlphaDynInst : public BaseDynInst #if FULL_SYSTEM /** Calls hardware return from error interrupt. */ Fault hwrei(); - /** Checks if system is in PAL mode. */ - bool inPalMode(); /** Traps to handle specified fault. */ void trap(Fault fault); bool simPalCheck(int palFunc); diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index f27cd5961..6fc548a85 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -113,7 +113,7 @@ Fault AlphaDynInst::hwrei() { // Can only do a hwrei when in pal mode. - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; // Set the next PC based on the value of the EXC_ADDR IPR. @@ -127,13 +127,6 @@ AlphaDynInst::hwrei() return NoFault; } -template -bool -AlphaDynInst::inPalMode() -{ - return this->cpu->inPalMode(this->PC); -} - template void AlphaDynInst::trap(Fault fault) diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh index f0cecee35..bcecb7087 100644 --- a/src/cpu/o3/alpha/thread_context.hh +++ b/src/cpu/o3/alpha/thread_context.hh @@ -47,11 +47,6 @@ class AlphaTC : public O3ThreadContext { return this->thread->quiesceEvent; } - - /** Returns if the thread is currently in PAL mode, based on - * the PC's value. */ - virtual bool inPalMode() - { return TheISA::PcPAL(this->cpu->readPC(this->thread->readTid())); } #endif virtual uint64_t readNextNPC() diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index ecf6ed632..bd5c4f9ce 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -638,8 +638,7 @@ DefaultCommit::commit() // and no other traps or external squashes are currently pending. // @todo: Allow other threads to handle interrupts. if (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode(readPC()) && + cpu->check_interrupts(cpu->tcBase(0)) && !trapSquash[0] && !tcSquash[0]) { // Tell fetch that there is an interrupt pending. This will diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 31f3b96d6..4c39341aa 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -559,14 +559,9 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid { Fault fault = NoFault; -#if FULL_SYSTEM - // Flag to say whether or not address is physical addr. - unsigned flags = cpu->inPalMode(fetch_PC) ? PHYSICAL : 0; -#else - unsigned flags = 0; -#endif // FULL_SYSTEM - - if (cacheBlocked || isSwitchedOut() || (interruptPending && flags == 0)) { + //AlphaDep + if (cacheBlocked || isSwitchedOut() || + (interruptPending && (fetch_PC & 0x3))) { // Hold off fetch from getting new instructions when: // Cache is blocked, or // while an interrupt is pending and we're not in PAL mode, or @@ -585,7 +580,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. // Build request here. - RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, flags, + RequestPtr mem_req = new Request(tid, fetch_PC, cacheBlkSize, 0, fetch_PC, cpu->readCpuId(), tid); memReq[tid] = mem_req; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 828c2b4ca..b3d3531e9 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -239,10 +239,6 @@ class OzoneCPU : public BaseCPU void setStCondFailures(unsigned sc_failures) { thread->storeCondFailures = sc_failures; } -#if FULL_SYSTEM - bool inPalMode() { return cpu->inPalMode(); } -#endif - bool misspeculating() { return false; } #if !FULL_SYSTEM @@ -584,8 +580,6 @@ class OzoneCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei(); - bool inPalMode() { return AlphaISA::PcPAL(thread.PC); } - bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); } bool simPalCheck(int palFunc); void processInterrupts(); #else diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh index 532317b08..9445a5309 100644 --- a/src/cpu/ozone/dyn_inst.hh +++ b/src/cpu/ozone/dyn_inst.hh @@ -238,7 +238,6 @@ class OzoneDynInst : public BaseDynInst #if FULL_SYSTEM Fault hwrei(); - bool inPalMode(); void trap(Fault fault); bool simPalCheck(int palFunc); #else diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 68736ae61..426841536 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -249,7 +249,7 @@ template Fault OzoneDynInst::hwrei() { - if (!this->cpu->inPalMode(this->readPC())) + if (!(this->readPC() & 0x3)) return new AlphaISA::UnimplementedOpcodeFault; this->setNextPC(this->thread->readMiscReg(AlphaISA::IPR_EXC_ADDR)); @@ -260,13 +260,6 @@ OzoneDynInst::hwrei() return NoFault; } -template -bool -OzoneDynInst::inPalMode() -{ - return this->cpu->inPalMode(); -} - template void OzoneDynInst::trap(Fault fault) diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh index 6d02c58cb..73ca6afbe 100644 --- a/src/cpu/ozone/front_end_impl.hh +++ b/src/cpu/ozone/front_end_impl.hh @@ -462,15 +462,10 @@ Fault FrontEnd::fetchCacheLine() { // Read a cache line, based on the current PC. -#if FULL_SYSTEM - // Flag to say whether or not address is physical addr. - unsigned flags = cpu->inPalMode(PC) ? PHYSICAL : 0; -#else - unsigned flags = 0; -#endif // FULL_SYSTEM Fault fault = NoFault; - if (interruptPending && flags == 0) { + //AlphaDep + if (interruptPending && (PC & 0x3)) { return fault; } diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh index 8aef9c074..87bf0a7a2 100644 --- a/src/cpu/ozone/inorder_back_end_impl.hh +++ b/src/cpu/ozone/inorder_back_end_impl.hh @@ -152,11 +152,11 @@ InorderBackEnd::tick() #if FULL_SYSTEM if (interruptBlocked || (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode())) { + cpu->check_interrupts(tc))) { if (!robEmpty()) { interruptBlocked = true; - } else if (robEmpty() && cpu->inPalMode()) { + //AlphaDep + } else if (robEmpty() && (PC & 0x3)) { // Will need to let the front end continue a bit until // we're out of pal mode. Hopefully we never get into an // infinite loop... diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index c39b9e08b..a181c93f4 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -526,8 +526,7 @@ void LWBackEnd::checkInterrupts() { if (cpu->checkInterrupts && - cpu->check_interrupts() && - !cpu->inPalMode(thread->readPC()) && + cpu->check_interrupts(tc) && !trapSquash && !tcSquash) { frontEnd->interruptPending = true; diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 0c7b5eafe..e91569db2 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -311,11 +311,11 @@ void BaseSimpleCPU::checkForInterrupts() { #if FULL_SYSTEM - if (checkInterrupts && check_interrupts() && !thread->inPalMode()) { - checkInterrupts = false; + if (checkInterrupts && check_interrupts(tc)) { Fault interrupt = interrupts.getInterrupt(tc); if (interrupt != NoFault) { + checkInterrupts = false; interrupt->invoke(tc); } } @@ -371,6 +371,10 @@ BaseSimpleCPU::preExecute() StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC())); #elif THE_ISA == SPARC_ISA StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC())); +#elif THE_ISA == MIPS_ISA + //Mips doesn't do anything in it's MakeExtMI function right now, + //so it won't be called. + StaticInstPtr instPtr = StaticInst::decode(inst); #endif if (instPtr->isMacroOp()) { curMacroStaticInst = instPtr; diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index d13be2877..efb884325 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -302,7 +302,6 @@ class BaseSimpleCPU : public BaseCPU #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } - bool inPalMode() { return thread->inPalMode(); } void ev5_trap(Fault fault) { fault->invoke(tc); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } #else diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 9a575f06b..600588295 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -440,10 +440,6 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } -#if FULL_SYSTEM - bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); } -#endif - #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index dfc6fbc2a..82d75b161 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -236,10 +236,6 @@ class ThreadContext virtual void setStCondFailures(unsigned sc_failures) = 0; -#if FULL_SYSTEM - virtual bool inPalMode() = 0; -#endif - // Only really makes sense for old CPU model. Still could be useful though. virtual bool misspeculating() = 0; @@ -424,9 +420,6 @@ class ProxyThreadContext : public ThreadContext void setStCondFailures(unsigned sc_failures) { actualTC->setStCondFailures(sc_failures); } -#if FULL_SYSTEM - bool inPalMode() { return actualTC->inPalMode(); } -#endif // @todo: Fix this! bool misspeculating() { return actualTC->misspeculating(); } -- cgit v1.2.3 From 4a5cb3f4250544cd5cdf423405d66471b33c545c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 3 Nov 2006 11:05:56 -0500 Subject: The tc needs to be protected instead of private so that the CpuEventWrapper can access it. --HG-- extra : convert_revision : bd836d63ac3630b20dda552e7b289730f3c114ef --- src/cpu/cpuevent.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/cpuevent.hh b/src/cpu/cpuevent.hh index 9dfae27cf..3339f8252 100644 --- a/src/cpu/cpuevent.hh +++ b/src/cpu/cpuevent.hh @@ -44,7 +44,7 @@ class ThreadContext; * */ class CpuEvent : public Event { - private: + protected: /** type of global list of cpu events. */ typedef std::vector CpuEventList; -- cgit v1.2.3 From 21cf4a46b9e9ce52266aac873aa107cad82cc847 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Sat, 4 Nov 2006 21:41:01 -0500 Subject: fixes so that M5 will compile under solaris SConstruct: Add check to see if we need to include libsocket src/arch/sparc/floatregfile.cc: src/arch/sparc/intregfile.cc: use memset rather than bzero and include the appropriate headerfile src/base/pollevent.cc: If we're compling under solaris we need sys/file.h src/base/random.cc: src/base/random.hh: solaris doesn't have random(), so use rint with the correct rounding mode if we're compiling on solaris src/base/stats/flags.hh: u_int32_t?? src/base/time.hh: grab the timersub() define from freebsd since it doesn't exist in solaris src/cpu/inst_seq.hh: we don't need to include stdint here src/sim/byteswap.hh: the method to detect endianness on Solaris is a little more complex... --HG-- extra : convert_revision : 6b7db0e900e7bccfc250d65c125065f27280dda1 --- src/cpu/inst_seq.hh | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/inst_seq.hh b/src/cpu/inst_seq.hh index e7acd215f..21e04ed25 100644 --- a/src/cpu/inst_seq.hh +++ b/src/cpu/inst_seq.hh @@ -32,8 +32,6 @@ #ifndef __STD_TYPES_HH__ #define __STD_TYPES_HH__ -#include - // inst sequence type, used to order instructions in the ready list, // if this rolls over the ready list order temporarily will get messed // up, but execution will continue and complete correctly -- cgit v1.2.3 From 067c9c5531cb591aa7a2472ebbe366683fcfeb0d Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sun, 5 Nov 2006 20:29:38 -0500 Subject: Initialize pointer to NULL. src/cpu/o3/lsq_unit_impl.hh: Be sure to initialize pointer to NULL. --HG-- extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a --- src/cpu/o3/lsq_unit_impl.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index d940d7cb3..9a0e48819 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -131,6 +131,7 @@ LSQUnit::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries, usedPorts = 0; cachePorts = params->cachePorts; + retryPkt = NULL; memDepViolator = NULL; blockedLoadSeqNum = 0; -- cgit v1.2.3 From 652281a61c6be7210b575e50566e7efdc82ab6ba Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 6 Nov 2006 13:27:45 -0500 Subject: Clean up clock phase drift code a bit. src/cpu/base.cc: Move clock phase drift code to the base CPU so that any CPU model can use it. src/cpu/base.hh: Added two functions to help get the next cycle the CPU should be scheduled. src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Use the function now in BaseCPU. --HG-- extra : convert_revision : 444494b66ffc85fc473c23f57683c5f9458ad80c --- src/cpu/base.cc | 20 ++++++++++++++++++++ src/cpu/base.hh | 14 ++++++++++++++ src/cpu/simple/atomic.cc | 12 +++--------- src/cpu/simple/timing.cc | 18 ++++++++---------- 4 files changed, 45 insertions(+), 19 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.cc b/src/cpu/base.cc index ea4b03bf2..55ceea8fb 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -259,6 +259,26 @@ BaseCPU::regStats() #endif } +Tick +BaseCPU::nextCycle() +{ + Tick next_tick = curTick + clock - 1; + next_tick -= (next_tick % clock); + return next_tick; +} + +Tick +BaseCPU::nextCycle(Tick begin_tick) +{ + Tick next_tick = begin_tick; + + while (next_tick < curTick) + next_tick += clock; + + next_tick -= (next_tick % clock); + assert(next_tick >= curTick); + return next_tick; +} void BaseCPU::registerThreadContexts() diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 75e0d86af..df665ed23 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -73,6 +73,20 @@ class BaseCPU : public MemObject inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } + /** The next cycle the CPU should be scheduled, given a cache + * access or quiesce event returning on this cycle. This function + * may return curTick if the CPU should run on the current cycle. + */ + Tick nextCycle(); + + /** The next cycle the CPU should be scheduled, given a cache + * access or quiesce event returning on the given Tick. This + * function may return curTick if the CPU should run on the + * current cycle. + * @param begin_tick The tick that the event is completing on. + */ + Tick nextCycle(Tick begin_tick); + #if FULL_SYSTEM protected: uint64_t interrupts[TheISA::NumInterruptLevels]; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 72249be41..4f68cfd6f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -180,9 +180,7 @@ AtomicSimpleCPU::resume() changeState(SimObject::Running); if (thread->status() == ThreadContext::Active) { if (!tickEvent.scheduled()) { - Tick nextTick = curTick + cycles(1) - 1; - nextTick -= (nextTick % (cycles(1))); - tickEvent.schedule(nextTick); + tickEvent.schedule(nextCycle()); } } } @@ -211,9 +209,7 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) ThreadContext *tc = threadContexts[i]; if (tc->status() == ThreadContext::Active && _status != Running) { _status = Running; - Tick nextTick = curTick + cycles(1) - 1; - nextTick -= (nextTick % (cycles(1))); - tickEvent.schedule(nextTick); + tickEvent.schedule(nextCycle()); break; } } @@ -231,9 +227,7 @@ AtomicSimpleCPU::activateContext(int thread_num, int delay) notIdleFraction++; //Make sure ticks are still on multiples of cycles - Tick nextTick = curTick + cycles(delay + 1) - 1; - nextTick -= (nextTick % (cycles(1))); - tickEvent.schedule(nextTick); + tickEvent.schedule(nextCycle(curTick + cycles(delay))); _status = Running; } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 4d57bf6d5..abf316095 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -532,14 +532,13 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick time = pkt->req->getTime(); - while (time < curTick) - time += lat; + Tick mem_time = pkt->req->getTime(); + Tick next_tick = cpu->nextCycle(mem_time); - if (time == curTick) + if (next_tick == curTick) cpu->completeIfetch(pkt); else - tickEvent.schedule(pkt, time); + tickEvent.schedule(pkt, next_tick); return true; } @@ -610,14 +609,13 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { // delay processing of returned data until next CPU clock edge - Tick time = pkt->req->getTime(); - while (time < curTick) - time += lat; + Tick mem_time = pkt->req->getTime(); + Tick next_tick = cpu->nextCycle(mem_time); - if (time == curTick) + if (next_tick == curTick) cpu->completeDataAccess(pkt); else - tickEvent.schedule(pkt, time); + tickEvent.schedule(pkt, next_tick); return true; } -- cgit v1.2.3 From 85a6079db7c2e7146dc437c9c032d2aa56dd9048 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 6 Nov 2006 18:29:58 -0500 Subject: Remote GDB support has been changed to use inheritance. Alpha should work, but isn't tested. Other architectures will not. --HG-- extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707 --- src/cpu/o3/fetch_impl.hh | 1 - 1 file changed, 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 4c39341aa..5ef6e27ea 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -45,7 +45,6 @@ #if FULL_SYSTEM #include "arch/tlb.hh" #include "arch/vtophys.hh" -#include "base/remote_gdb.hh" #include "sim/system.hh" #endif // FULL_SYSTEM -- cgit v1.2.3 From 4bfb8547bbdee3bd0ec23ae067ff04fd5e07f4be Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:36:54 -0500 Subject: Moved the switched version of kernel_stats.hh back to kern, and moved the base kernel_stats to base_kernel_stats --HG-- extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017 --- src/cpu/checker/thread_context.hh | 9 ++++++--- src/cpu/o3/thread_context.hh | 2 +- src/cpu/o3/thread_context_impl.hh | 2 +- src/cpu/ozone/cpu.hh | 8 +++++--- src/cpu/ozone/cpu_impl.hh | 2 +- src/cpu/simple_thread.cc | 6 +++--- src/cpu/simple_thread.hh | 6 ++++-- src/cpu/thread_context.hh | 11 +++++++---- src/cpu/thread_state.hh | 10 ++++++---- 9 files changed, 34 insertions(+), 22 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh index b46031167..cf36d8392 100644 --- a/src/cpu/checker/thread_context.hh +++ b/src/cpu/checker/thread_context.hh @@ -37,8 +37,10 @@ #include "cpu/thread_context.hh" class EndQuiesceEvent; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; /** @@ -91,7 +93,8 @@ class CheckerThreadContext : public ThreadContext TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } - Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } + TheISA::Kernel::Statistics *getKernelStats() + { return actualTC->getKernelStats(); } FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 4556c5e22..daee2fc7d 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -83,7 +83,7 @@ class O3ThreadContext : public ThreadContext virtual PhysicalMemory *getPhysMemPtr() { return cpu->physmem; } /** Returns a pointer to this thread's kernel statistics. */ - virtual Kernel::Statistics *getKernelStats() + virtual TheISA::Kernel::Statistics *getKernelStats() { return thread->kernelStats; } virtual FunctionalPort *getPhysPort() { return thread->getPhysPort(); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 81750ada7..8d623f5b8 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -194,7 +194,7 @@ void O3ThreadContext::regStats(const std::string &name) { #if FULL_SYSTEM - thread->kernelStats = new Kernel::Statistics(cpu->system); + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats->regStats(name + ".kern"); #endif } diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index b3d3531e9..2b2ed7b3e 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -62,8 +62,10 @@ class MemoryController; class RemoteGDB; class GDBListener; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; #else @@ -127,7 +129,7 @@ class OzoneCPU : public BaseCPU TheISA::DTB * getDTBPtr() { return cpu->dtb; } - Kernel::Statistics *getKernelStats() + TheISA::Kernel::Statistics *getKernelStats() { return thread->getKernelStats(); } FunctionalPort *getPhysPort() { return thread->getPhysPort(); } diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 6f5dede3e..b83cf4e9e 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -891,7 +891,7 @@ void OzoneCPU::OzoneTC::regStats(const std::string &name) { #if FULL_SYSTEM - thread->kernelStats = new Kernel::Statistics(cpu->system); + thread->kernelStats = new TheISA::Kernel::Statistics(cpu->system); thread->kernelStats->regStats(name + ".kern"); #endif } diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 8bb4ec46b..5ae1e1d3c 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -87,7 +87,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, profilePC = 3; if (use_kernel_stats) { - kernelStats = new Kernel::Statistics(system); + kernelStats = new TheISA::Kernel::Statistics(system); } else { kernelStats = NULL; } @@ -158,7 +158,7 @@ SimpleThread::takeOverFrom(ThreadContext *oldContext) quiesceEvent->tc = tc; } - Kernel::Statistics *stats = oldContext->getKernelStats(); + TheISA::Kernel::Statistics *stats = oldContext->getKernelStats(); if (stats) { kernelStats = stats; } @@ -179,7 +179,7 @@ SimpleThread::copyTC(ThreadContext *context) if (quiesce) { quiesceEvent = quiesce; } - Kernel::Statistics *stats = context->getKernelStats(); + TheISA::Kernel::Statistics *stats = context->getKernelStats(); if (stats) { kernelStats = stats; } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 600588295..e8757c8c2 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -55,8 +55,10 @@ class ProfileNode; class FunctionalPort; class PhysicalPort; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; #else // !FULL_SYSTEM diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 82d75b161..1e6a907f8 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -56,8 +56,10 @@ class FunctionalPort; class VirtualPort; class Process; class System; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; /** @@ -124,7 +126,7 @@ class ThreadContext virtual TheISA::DTB *getDTBPtr() = 0; - virtual Kernel::Statistics *getKernelStats() = 0; + virtual TheISA::Kernel::Statistics *getKernelStats() = 0; virtual FunctionalPort *getPhysPort() = 0; @@ -295,7 +297,8 @@ class ProxyThreadContext : public ThreadContext TheISA::DTB *getDTBPtr() { return actualTC->getDTBPtr(); } - Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); } + TheISA::Kernel::Statistics *getKernelStats() + { return actualTC->getKernelStats(); } FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 862d671f2..0a0af8b71 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -44,8 +44,10 @@ class EndQuiesceEvent; class FunctionProfile; class ProfileNode; -namespace Kernel { - class Statistics; +namespace TheISA { + namespace Kernel { + class Statistics; + }; }; #endif @@ -97,7 +99,7 @@ struct ThreadState { void profileSample(); - Kernel::Statistics *getKernelStats() { return kernelStats; } + TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; } FunctionalPort *getPhysPort() { return physPort; } @@ -187,7 +189,7 @@ struct ThreadState { Addr profilePC; EndQuiesceEvent *quiesceEvent; - Kernel::Statistics *kernelStats; + TheISA::Kernel::Statistics *kernelStats; protected: /** A functional port outgoing only for functional accesses to physical * addresses.*/ -- cgit v1.2.3 From 3826b6927c5c8863b344f1a36f2f145861c450bd Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:41:51 -0500 Subject: Got rid of a stray blank line. --HG-- extra : convert_revision : 7b58f75e5efc3c9ead2434f87605cbabcb23d90a --- src/cpu/o3/regfile.hh | 1 - 1 file changed, 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 29ee19e49..772cd76f0 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -40,7 +40,6 @@ #if FULL_SYSTEM #include "kern/kernel_stats.hh" - #endif #include -- cgit v1.2.3 From 2f4c66ad2d1ddf7c3295cd176ce39aa4d3fcb816 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 05:42:15 -0500 Subject: Added sim/host.hh for the Addr type. --HG-- extra : convert_revision : cd07a920417b7fb34e5ca3bf70d707327eb59eb3 --- src/cpu/pc_event.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh index 6b048b2c2..3709dcd59 100644 --- a/src/cpu/pc_event.hh +++ b/src/cpu/pc_event.hh @@ -35,6 +35,7 @@ #include #include "base/misc.hh" +#include "sim/host.hh" class ThreadContext; class PCEventQueue; -- cgit v1.2.3 From d9f159a3b996b25683f33bcc8ae5142311639722 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Nov 2006 13:53:06 -0500 Subject: Initialize mem dep unit properly. src/cpu/o3/mem_dep_unit_impl.hh: Initialize mem dep unit properly, add debug output. --HG-- extra : convert_revision : 3c56dedfa57de1edc4b1c8f8d9bc94e18002eff2 --- src/cpu/o3/mem_dep_unit.hh | 2 +- src/cpu/o3/mem_dep_unit_impl.hh | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index e399f0133..a12a3001b 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -69,7 +69,7 @@ class MemDepUnit { typedef typename Impl::DynInstPtr DynInstPtr; /** Empty constructor. Must call init() prior to using in this case. */ - MemDepUnit() {} + MemDepUnit(); /** Constructs a MemDepUnit with given parameters. */ MemDepUnit(Params *params); diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh index c649ca385..f19980fd5 100644 --- a/src/cpu/o3/mem_dep_unit_impl.hh +++ b/src/cpu/o3/mem_dep_unit_impl.hh @@ -33,6 +33,13 @@ #include "cpu/o3/inst_queue.hh" #include "cpu/o3/mem_dep_unit.hh" +template +MemDepUnit::MemDepUnit() + : loadBarrier(false), loadBarrierSN(0), storeBarrier(false), + storeBarrierSN(0), iqPtr(NULL) +{ +} + template MemDepUnit::MemDepUnit(Params *params) : depPred(params->SSITSize, params->LFSTSize), loadBarrier(false), @@ -160,8 +167,12 @@ MemDepUnit::insert(DynInstPtr &inst) // producing memrefs/stores. InstSeqNum producing_store; if (inst->isLoad() && loadBarrier) { + DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n", + loadBarrierSN); producing_store = loadBarrierSN; } else if (inst->isStore() && storeBarrier) { + DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n", + storeBarrierSN); producing_store = storeBarrierSN; } else { producing_store = depPred.checkInst(inst->readPC()); @@ -171,10 +182,12 @@ MemDepUnit::insert(DynInstPtr &inst) // If there is a producing store, try to find the entry. if (producing_store != 0) { + DPRINTF(MemDepUnit, "Searching for producer\n"); MemDepHashIt hash_it = memDepHash.find(producing_store); if (hash_it != memDepHash.end()) { store_entry = (*hash_it).second; + DPRINTF(MemDepUnit, "Proucer found\n"); } } -- cgit v1.2.3 From 4589ec55aed596a4b0b7d81779f2b4665643d223 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Tue, 7 Nov 2006 13:53:49 -0500 Subject: Fix compile error. --HG-- extra : convert_revision : a4c4195bc07383149a56907f26d327a4bfa77c26 --- src/cpu/ozone/cpu.hh | 4 ++-- src/cpu/ozone/thread_state.hh | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index 828c2b4ca..ccb467394 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -363,8 +363,8 @@ class OzoneCPU : public BaseCPU bool interval_stats; - AlphaITB *itb; - AlphaDTB *dtb; + TheISA::ITB *itb; + TheISA::DTB *dtb; System *system; PhysicalMemory *physmem; #endif diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index c4d16b3af..a71795851 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState { MiscReg readMiscRegWithEffect(int misc_reg) { - return miscRegFile.readRegWithEffect(misc_reg, fault, tc); + return miscRegFile.readRegWithEffect(misc_reg, tc); } void setMiscReg(int misc_reg, const MiscReg &val) -- cgit v1.2.3 From f7a35c33d70d99c1276a70c2ed1a86719e64973b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 7 Nov 2006 15:51:37 -0500 Subject: add code to operate in lockstep with legion src/python/m5/main.py: add option to operate in lockstep with legion --HG-- extra : convert_revision : 2cc90ec0cf7e8d028ee813c2034a77415671a628 --- src/cpu/exetrace.cc | 92 ++++++++++++++++++++++++++++++++++++++++++++ src/cpu/exetrace.hh | 1 + src/cpu/m5legion_interface.h | 50 ++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 src/cpu/m5legion_interface.h (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 9d85311bb..80b144e85 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -33,6 +33,8 @@ #include #include +#include +#include #include "arch/regfile.hh" #include "base/loader/symtab.hh" @@ -44,10 +46,15 @@ //XXX This is temporary #include "arch/isa_specific.hh" +#include "cpu/m5legion_interface.h" using namespace std; using namespace TheISA; +namespace Trace { +SharedData *shared_data = NULL; +} + //////////////////////////////////////////////////////////////////////// // // Methods for the InstRecord object @@ -60,6 +67,7 @@ Trace::InstRecord::dump(ostream &outs) if (flags[PRINT_REG_DELTA]) { #if THE_ISA == SPARC_ISA +#if 0 //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) @@ -120,6 +128,7 @@ Trace::InstRecord::dump(ostream &outs) } outs << endl; } +#endif #endif } else if (flags[INTEL_FORMAT]) { @@ -222,6 +231,65 @@ Trace::InstRecord::dump(ostream &outs) // outs << endl; } + // Compare + if (flags[LEGION_LOCKSTEP]) + { + bool compared = false; + bool diffPC = false; + bool diffInst = false; + bool diffRegs = false; + + while (!compared) { + if (shared_data->flags == OWN_M5) { + if (shared_data->pc != PC) + diffPC = true; + if (shared_data->instruction != staticInst->machInst) + diffInst = true; + for (int i = 0; i < TheISA::NumIntRegs; i++) { + if (thread->readIntReg(i) != shared_data->intregs[i]) + diffRegs = true; + } + + if (diffPC || diffInst || diffRegs ) { + outs << "Differences found between M5 and Legion:"; + if (diffPC) + outs << " PC"; + if (diffInst) + outs << " Instruction"; + if (diffRegs) + outs << " IntRegs"; + outs << endl; + + outs << "M5 PC: " << setw(20) << "0x" << hex << PC; + outs << "Legion PC: " << setw(20) << "0x" << hex << + shared_data->pc << endl; + + + + outs << "M5 Instruction: " << staticInst->machInst << "(" + << staticInst->disassemble(PC, debugSymbolTable) + << ")" << "Legion Instruction: " << + shared_data->instruction << "(" + /*<< legionInst->disassemble(shared_data->pc, + debugSymbolTable)*/ + << ")" << endl; + + for (int i = 0; i < TheISA::NumIntRegs; i++) { + outs << setw(16) << "0x" << hex << thread->readIntReg(i) + << setw(16) << "0x" << hex << shared_data->intregs[i]; + + if (thread->readIntReg(i) != shared_data->intregs[i]) + outs << "<--- Different"; + outs << endl; + } + } + + compared = true; + shared_data->flags = OWN_LEGION; + } + } + + } } @@ -271,6 +339,9 @@ Param exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", "Use symbols for the PC if available", true); Param exe_trace_intel_format(&exeTraceParams, "intel_format", "print trace in intel compatible format", false); +Param exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", + "Compare sim state to legion state every cycle", + false); Param exe_trace_system(&exeTraceParams, "trace_system", "print trace of which system (client or server)", "client"); @@ -296,7 +367,28 @@ Trace::InstRecord::setParams() flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; flags[PC_SYMBOL] = exe_trace_pc_symbol; flags[INTEL_FORMAT] = exe_trace_intel_format; + flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; trace_system = exe_trace_system; + + // If were going to be in lockstep with Legion + // Setup shared memory, and get otherwise ready + if (flags[LEGION_LOCKSTEP]) { + int shmfd = shmget(getuid(), sizeof(SharedData), 0777); + if (shmfd < 0) + fatal("Couldn't get shared memory fd. Is Legion running?"); + + shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); + if (shared_data == (SharedData*)-1) + fatal("Couldn't allocate shared memory"); + + if (shared_data->flags != OWN_M5) + fatal("Shared memory has invalid owner"); + + if (shared_data->version != VERSION) + fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, + shared_data->version); + + } } void diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh index 02ea162f0..6562e5265 100644 --- a/src/cpu/exetrace.hh +++ b/src/cpu/exetrace.hh @@ -150,6 +150,7 @@ class InstRecord : public Record PRINT_REG_DELTA, PC_SYMBOL, INTEL_FORMAT, + LEGION_LOCKSTEP, NUM_BITS }; diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h new file mode 100644 index 000000000..0fa0e7279 --- /dev/null +++ b/src/cpu/m5legion_interface.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Ali Saidi + */ + +#include + +#define VERSION 0xA1000001 +#define OWN_M5 0x000000AA +#define OWN_LEGION 0x00000055 + +/** !!! VVV Increment VERSION on change VVV !!! **/ + +typedef struct { + uint32_t flags; + uint32_t version; + + uint64_t pc; + uint64_t instruction; + uint64_t intregs[32]; + +} SharedData; + +/** !!! ^^^ Increment VERSION on change ^^^ !!! **/ + -- cgit v1.2.3 From a05b16b1ab56d55bb7400f0cb1eaa466905f43d5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 20:26:45 -0500 Subject: Only include kern/kernel_stats.hh if in full system. This was breaking MIPS_SE --HG-- extra : convert_revision : b3f956af92cb98b4945aebc8aece1dffcabdf15c --- src/cpu/simple/base.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index e91569db2..b7df39218 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -46,7 +46,6 @@ #include "cpu/smt.hh" #include "cpu/static_inst.hh" #include "cpu/thread_context.hh" -#include "kern/kernel_stats.hh" #include "mem/packet.hh" #include "sim/builder.hh" #include "sim/byteswap.hh" @@ -58,10 +57,11 @@ #include "sim/system.hh" #if FULL_SYSTEM -#include "base/remote_gdb.hh" #include "arch/tlb.hh" #include "arch/stacktrace.hh" #include "arch/vtophys.hh" +#include "base/remote_gdb.hh" +#include "kern/kernel_stats.hh" #else // !FULL_SYSTEM #include "mem/mem_object.hh" #endif // FULL_SYSTEM -- cgit v1.2.3 From c693c6ba9f9d641344db8a2a505484f5f8aa2645 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 7 Nov 2006 22:34:34 -0500 Subject: Put kernel_stats back into arch. --HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966 --- src/cpu/checker/cpu.cc | 2 +- src/cpu/o3/alpha/cpu_impl.hh | 2 +- src/cpu/o3/regfile.hh | 2 +- src/cpu/ozone/cpu_impl.hh | 6 +++--- src/cpu/ozone/dyn_inst_impl.hh | 3 +++ src/cpu/simple/base.cc | 4 ++-- src/cpu/simple_thread.cc | 2 +- src/cpu/thread_state.cc | 2 +- 8 files changed, 13 insertions(+), 10 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 2e81b7b31..d6cd9409b 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -38,8 +38,8 @@ #include "cpu/thread_context.hh" #if FULL_SYSTEM +#include "arch/kernel_stats.hh" #include "arch/vtophys.hh" -#include "kern/kernel_stats.hh" #endif // FULL_SYSTEM using namespace std; diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh index 750ccc912..04eadfa5a 100644 --- a/src/cpu/o3/alpha/cpu_impl.hh +++ b/src/cpu/o3/alpha/cpu_impl.hh @@ -48,8 +48,8 @@ #if FULL_SYSTEM #include "arch/alpha/osfpal.hh" #include "arch/isa_traits.hh" +#include "arch/kernel_stats.hh" #include "cpu/quiesce_event.hh" -#include "kern/kernel_stats.hh" #include "sim/sim_exit.hh" #include "sim/system.hh" #endif diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 772cd76f0..598af123e 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -39,7 +39,7 @@ #include "cpu/o3/comm.hh" #if FULL_SYSTEM -#include "kern/kernel_stats.hh" +#include "arch/kernel_stats.hh" #endif #include diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index b83cf4e9e..86c973a0f 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -47,12 +47,12 @@ #if FULL_SYSTEM #include "arch/faults.hh" #include "arch/alpha/osfpal.hh" -#include "arch/alpha/tlb.hh" -#include "arch/alpha/types.hh" +#include "arch/tlb.hh" +#include "arch/types.hh" +#include "arch/kernel_stats.hh" #include "arch/vtophys.hh" #include "base/callback.hh" #include "cpu/profile.hh" -#include "kern/kernel_stats.hh" #include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index 426841536..05a66d77a 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -31,7 +31,10 @@ #include "sim/faults.hh" #include "config/full_system.hh" #include "cpu/ozone/dyn_inst.hh" + +#if FULL_SYSTEM #include "kern/kernel_stats.hh" +#endif template OzoneDynInst::OzoneDynInst(OzoneCPU *cpu) diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index b7df39218..00fa4d247 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -57,11 +57,11 @@ #include "sim/system.hh" #if FULL_SYSTEM -#include "arch/tlb.hh" +#include "arch/kernel_stats.hh" #include "arch/stacktrace.hh" +#include "arch/tlb.hh" #include "arch/vtophys.hh" #include "base/remote_gdb.hh" -#include "kern/kernel_stats.hh" #else // !FULL_SYSTEM #include "mem/mem_object.hh" #endif // FULL_SYSTEM diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 5ae1e1d3c..1edcbf352 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -39,13 +39,13 @@ #include "cpu/thread_context.hh" #if FULL_SYSTEM +#include "arch/kernel_stats.hh" #include "base/callback.hh" #include "base/cprintf.hh" #include "base/output.hh" #include "base/trace.hh" #include "cpu/profile.hh" #include "cpu/quiesce_event.hh" -#include "kern/kernel_stats.hh" #include "sim/serialize.hh" #include "sim/sim_exit.hh" #include "arch/stacktrace.hh" diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc index a6fff5fc3..8602f8a50 100644 --- a/src/cpu/thread_state.cc +++ b/src/cpu/thread_state.cc @@ -37,8 +37,8 @@ #include "sim/serialize.hh" #if FULL_SYSTEM +#include "arch/kernel_stats.hh" #include "cpu/quiesce_event.hh" -#include "kern/kernel_stats.hh" #endif #if FULL_SYSTEM -- cgit v1.2.3 From f1a55570d305dd15d7bc9667453a0ca14bf16462 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 00:52:04 -0500 Subject: Put the ProcessInfo and StackTrace objects into the ISA namespaces. --HG-- extra : convert_revision : 1626703583f02a1c9823874290462c1b6bdb6c3c --- src/cpu/profile.hh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh index 7f9625241..27bb4efec 100644 --- a/src/cpu/profile.hh +++ b/src/cpu/profile.hh @@ -33,9 +33,9 @@ #include +#include "arch/stacktrace.hh" #include "cpu/static_inst.hh" #include "sim/host.hh" -#include "arch/stacktrace.hh" class ThreadContext; @@ -66,7 +66,7 @@ class FunctionProfile const SymbolTable *symtab; ProfileNode top; std::map pc_count; - StackTrace trace; + TheISA::StackTrace trace; public: FunctionProfile(const SymbolTable *symtab); -- cgit v1.2.3 From 67b9a2ebd850b6b0a01324b46ac3d6f87b3a8cb5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Nov 2006 13:55:48 -0500 Subject: Move the check to see if you're in user mode into the isa directory. --HG-- extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6 --- src/cpu/o3/commit_impl.hh | 4 ++-- src/cpu/simple/base.cc | 3 +-- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index bd5c4f9ce..30052a148 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -35,6 +35,7 @@ #include #include +#include "arch/utility.hh" #include "base/loader/symtab.hh" #include "base/timebuf.hh" #include "cpu/exetrace.hh" @@ -1084,8 +1085,7 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) #if FULL_SYSTEM if (thread[tid]->profile) { -// bool usermode = -// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0; +// bool usermode = TheISA::inUserMode(thread[tid]->getTC()); // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); thread[tid]->profilePC = head_inst->readPC(); ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 00fa4d247..ab438aa77 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -407,8 +407,7 @@ BaseSimpleCPU::postExecute() { #if FULL_SYSTEM if (thread->profile) { - bool usermode = - (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; + bool usermode = TheISA::inUserMode(tc); thread->profilePC = usermode ? 1 : thread->readPC(); ProfileNode *node = thread->profile->consume(tc, inst); if (node) -- cgit v1.2.3 From cb172d0332ecf4ff7f6329f1172d8e1cf78767e2 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 9 Nov 2006 18:22:46 -0500 Subject: Get SPARC to the point that it starts running. Add ability to load the ROM bin files, cleanup lockstep printing a bit Since we don't have a platform yet, you need to comment out the default responder stuff in Bus.py to make it work. SConstruct: Add TARGET_ISA to the list of environment variables that end up in the build_env for python configs/common/FSConfig.py: add a simple SPARC system to being testing with, you'll need to change makeLinuxAlphaSystem to makeSparcSystem in fs.py for now src/SConscript: add a raw file object, at least until we get more info about how to compile openboot properly src/arch/sparc/system.cc: src/arch/sparc/system.hh: add parameters for ROM files (OBP/Reset/Hypervisor), a ROM, load files into ROM src/base/loader/object_file.cc: src/base/loader/object_file.hh: add option to try raw when nothing works src/cpu/exetrace.cc: cleanup lockstep printing a little bit src/cpu/m5legion_interface.h: change the instruction to be 32 bits because it is src/mem/physical.cc: fix assert that doesn't work if memory starts somewhere above 0 src/python/m5/objects/BaseCPU.py: Add if statement to choose between sparc tlbs and alpha tlbs src/python/m5/objects/System.py: Add a sparc system that sets the rom addresses correctly src/python/m5/params.py: add the ability to add Addr() together --HG-- extra : convert_revision : bbbd8a56134f2dda2728091f740e2f7119b0c4af --- src/cpu/exetrace.cc | 111 +++++++++++++++++++++++++------------------ src/cpu/m5legion_interface.h | 4 +- 2 files changed, 68 insertions(+), 47 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 80b144e85..881fbbd9b 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -37,6 +37,7 @@ #include #include "arch/regfile.hh" +#include "arch/utility.hh" #include "base/loader/symtab.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" @@ -231,6 +232,7 @@ Trace::InstRecord::dump(ostream &outs) // outs << endl; } +#if THE_ISA == SPARC_ISA // Compare if (flags[LEGION_LOCKSTEP]) { @@ -239,57 +241,76 @@ Trace::InstRecord::dump(ostream &outs) bool diffInst = false; bool diffRegs = false; - while (!compared) { - if (shared_data->flags == OWN_M5) { - if (shared_data->pc != PC) - diffPC = true; - if (shared_data->instruction != staticInst->machInst) - diffInst = true; - for (int i = 0; i < TheISA::NumIntRegs; i++) { - if (thread->readIntReg(i) != shared_data->intregs[i]) - diffRegs = true; - } - - if (diffPC || diffInst || diffRegs ) { - outs << "Differences found between M5 and Legion:"; - if (diffPC) - outs << " PC"; - if (diffInst) - outs << " Instruction"; - if (diffRegs) - outs << " IntRegs"; - outs << endl; - - outs << "M5 PC: " << setw(20) << "0x" << hex << PC; - outs << "Legion PC: " << setw(20) << "0x" << hex << - shared_data->pc << endl; - - - - outs << "M5 Instruction: " << staticInst->machInst << "(" - << staticInst->disassemble(PC, debugSymbolTable) - << ")" << "Legion Instruction: " << - shared_data->instruction << "(" - /*<< legionInst->disassemble(shared_data->pc, - debugSymbolTable)*/ - << ")" << endl; - + if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) { + while (!compared) { + if (shared_data->flags == OWN_M5) { + if (shared_data->pc != PC) + diffPC = true; + if (shared_data->instruction != staticInst->machInst) + diffInst = true; for (int i = 0; i < TheISA::NumIntRegs; i++) { - outs << setw(16) << "0x" << hex << thread->readIntReg(i) - << setw(16) << "0x" << hex << shared_data->intregs[i]; - if (thread->readIntReg(i) != shared_data->intregs[i]) - outs << "<--- Different"; - outs << endl; + diffRegs = true; } - } - compared = true; - shared_data->flags = OWN_LEGION; - } - } + if (diffPC || diffInst || diffRegs ) { + outs << "Differences found between M5 and Legion:"; + if (diffPC) + outs << " [PC]"; + if (diffInst) + outs << " [Instruction]"; + if (diffRegs) + outs << " [IntRegs]"; + outs << endl << endl;; + + outs << setfill(' ') << setw(15) + << "M5 PC: " << "0x"<< setw(16) << setfill('0') + << hex << PC << endl; + outs << setfill(' ') << setw(15) + << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex + << shared_data->pc << endl << endl; + + outs << setfill(' ') << setw(15) + << "M5 Inst: " << "0x"<< setw(8) + << setfill('0') << hex << staticInst->machInst + << staticInst->disassemble(PC, debugSymbolTable) + << endl; + + StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread)); + outs << setfill(' ') << setw(15) + << " Legion Inst: " + << "0x" << setw(8) << setfill('0') << hex + << shared_data->instruction + << legionInst->disassemble(shared_data->pc, debugSymbolTable) + << endl; + + outs << endl; + static const char * regtypes[4] = {"%g", "%o", "%l", "%i"}; + for(int y = 0; y < 4; y++) + { + for(int x = 0; x < 8; x++) + { + outs << regtypes[y] << x << " " ; + outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x); + if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x]) + outs << " X "; + else + outs << " | "; + outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x] + << endl; + } + } + fatal("Differences found between Legion and M5\n"); + } + + compared = true; + shared_data->flags = OWN_LEGION; + } + } // while + } // if not microop } +#endif } diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index 0fa0e7279..9338d9ca0 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include -#define VERSION 0xA1000001 +#define VERSION 0xA1000002 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -41,7 +41,7 @@ typedef struct { uint32_t version; uint64_t pc; - uint64_t instruction; + uint32_t instruction; uint64_t intregs[32]; } SharedData; -- cgit v1.2.3 From 1d70dda6d72c4b563a19f3b4159a658d14b0eb41 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 10 Nov 2006 04:11:46 -0500 Subject: Change exetrace code for working with my trace tool to use stream io rather than sprintf which was breaking on 64 bit hosts. --HG-- extra : convert_revision : 184d751392dfcc8c80ac1a6c0ebc3061ff0a3f20 --- src/cpu/exetrace.cc | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 881fbbd9b..ef06e0699 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -68,7 +68,6 @@ Trace::InstRecord::dump(ostream &outs) if (flags[PRINT_REG_DELTA]) { #if THE_ISA == SPARC_ISA -#if 0 //Don't print what happens for each micro-op, just print out //once at the last op, and for regular instructions. if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) @@ -84,23 +83,19 @@ Trace::InstRecord::dump(ostream &outs) uint64_t newVal; static const char * prefixes[4] = {"G", "O", "L", "I"}; - char buf[256]; - sprintf(buf, "PC = 0x%016llx", thread->readNextPC()); - outs << buf; - sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC()); - outs << buf; + outs << hex; + outs << "PC = " << thread->readNextPC(); + outs << " NPC = " << thread->readNextNPC(); newVal = thread->readMiscReg(SparcISA::MISCREG_CCR); if(newVal != ccr) { - sprintf(buf, " CCR = 0x%016llx", newVal); - outs << buf; + outs << " CCR = " << newVal; ccr = newVal; } newVal = thread->readMiscReg(SparcISA::MISCREG_Y); if(newVal != y) { - sprintf(buf, " Y = 0x%016llx", newVal); - outs << buf; + outs << " Y = " << newVal; y = newVal; } for(int y = 0; y < 4; y++) @@ -111,8 +106,7 @@ Trace::InstRecord::dump(ostream &outs) newVal = thread->readIntReg(index); if(regs[index] != newVal) { - sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal); - outs << buf; + outs << " " << prefixes[y] << dec << x << " = " << hex << newVal; regs[index] = newVal; } } @@ -122,14 +116,12 @@ Trace::InstRecord::dump(ostream &outs) newVal = thread->readFloatRegBits(2 * y, 64); if(floats[y] != newVal) { - sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal); - outs << buf; + outs << " F" << dec << (2 * y) << " = " << hex << newVal; floats[y] = newVal; } } - outs << endl; + outs << dec << endl; } -#endif #endif } else if (flags[INTEL_FORMAT]) { -- cgit v1.2.3