From ca89eba79ebe0adc9cea7656c288e0381754171a Mon Sep 17 00:00:00 2001
From: Matt Horsnell <matt.horsnell@ARM.com>
Date: Fri, 24 Jan 2014 15:29:30 -0600
Subject: mem: track per-request latencies and access depths in the cache
 hierarchy

Add some values and methods to the request object to track the translation
and access latency for a request and which level of the cache hierarchy responded
to the request.
---
 src/cpu/o3/fetch_impl.hh    | 1 +
 src/cpu/o3/lsq_unit_impl.hh | 2 ++
 src/cpu/simple/timing.cc    | 6 +++++-
 src/cpu/translation.hh      | 1 +
 4 files changed, 9 insertions(+), 1 deletion(-)

(limited to 'src/cpu')

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index b35dd80f3..b121ba707 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -400,6 +400,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
         fetchStatus[tid] = IcacheAccessComplete;
     }
 
+    pkt->req->setAccessLatency();
     // Reset the mem req to NULL.
     delete pkt->req;
     delete pkt;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 77b67ac69..ade076995 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -129,6 +129,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         delete state->mainPkt->req;
         delete state->mainPkt;
     }
+
+    pkt->req->setAccessLatency();
     delete state;
     delete pkt->req;
     delete pkt;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 744bf8397..9253d8005 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -646,7 +646,6 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 
     // received a response from the icache: execute the received
     // instruction
-
     assert(!pkt || !pkt->isError());
     assert(_status == IcacheWaitResponse);
 
@@ -655,6 +654,10 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
     numCycles += curCycle() - previousCycle;
     previousCycle = curCycle();
 
+    if (pkt)
+        pkt->req->setAccessLatency();
+
+
     preExecute();
     if (curStaticInst && curStaticInst->isMemRef()) {
         // load or store: just send to dcache
@@ -749,6 +752,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
     assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
            pkt->req->getFlags().isSet(Request::NO_ACCESS));
 
+    pkt->req->setAccessLatency();
     numCycles += curCycle() - previousCycle;
     previousCycle = curCycle();
 
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 90fffa03d..c05cc86a0 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -256,6 +256,7 @@ class DataTranslation : public BaseTLB::Translation
         assert(mode == state->mode);
         if (state->finish(fault, index)) {
             xc->finishTranslation(state);
+            req->setTranslateLatency();
         }
         delete this;
     }
-- 
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