From c2dbfc1d6ca677f9b6fb8eaa60e4003a903e26bd Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 9 Jan 2012 18:08:20 -0600 Subject: MAC: Make gem5 compile and run on MacOSX 10.7.2 Adaptations to make gem5 compile and run on OSX 10.7.2, with a stock gcc 4.2.1 and the remaining dependencies from macports, i.e. python 2.7,.2 swig 2.0.4, mercurial 2.0. The changes include an adaptation of the SConstruct to handle non-library linker flags, and Darwin-specific code to find the memory usage of gem5. A number of Ruby files relied on ambigious uint (without the 32 suffix) which caused compilation errors. --- src/cpu/testers/directedtest/DirectedGenerator.hh | 2 +- src/cpu/testers/directedtest/InvalidateGenerator.cc | 2 +- src/cpu/testers/directedtest/InvalidateGenerator.hh | 8 ++++---- src/cpu/testers/directedtest/RubyDirectedTester.hh | 4 ++-- src/cpu/testers/directedtest/SeriesRequestGenerator.cc | 2 +- src/cpu/testers/directedtest/SeriesRequestGenerator.hh | 6 +++--- 6 files changed, 12 insertions(+), 12 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh index 904dcf399..c156efff0 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.hh +++ b/src/cpu/testers/directedtest/DirectedGenerator.hh @@ -43,7 +43,7 @@ class DirectedGenerator : public SimObject virtual ~DirectedGenerator() {} virtual bool initiate() = 0; - virtual void performCallback(uint proc, Addr address) = 0; + virtual void performCallback(uint32_t proc, Addr address) = 0; void setDirectedTester(RubyDirectedTester* directed_tester); diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 902c6cc15..4d8271a05 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -103,7 +103,7 @@ InvalidateGenerator::initiate() } void -InvalidateGenerator::performCallback(uint proc, Addr address) +InvalidateGenerator::performCallback(uint32_t proc, Addr address) { assert(m_address == address); diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.hh b/src/cpu/testers/directedtest/InvalidateGenerator.hh index 14c47b70b..50db180e3 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.hh +++ b/src/cpu/testers/directedtest/InvalidateGenerator.hh @@ -49,14 +49,14 @@ class InvalidateGenerator : public DirectedGenerator ~InvalidateGenerator(); bool initiate(); - void performCallback(uint proc, Addr address); + void performCallback(uint32_t proc, Addr address); private: InvalidateGeneratorStatus m_status; Addr m_address; - uint m_active_read_node; - uint m_active_inv_node; - uint m_addr_increment_size; + uint32_t m_active_read_node; + uint32_t m_active_inv_node; + uint32_t m_addr_increment_size; }; #endif //__CPU_DIRECTEDTEST_INVALIDATEGENERATOR_HH__ diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.hh b/src/cpu/testers/directedtest/RubyDirectedTester.hh index 163c206d8..53c389692 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh @@ -53,11 +53,11 @@ class RubyDirectedTester : public MemObject RubyDirectedTester *tester; public: - CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint _idx) + CpuPort(const std::string &_name, RubyDirectedTester *_tester, uint32_t _idx) : SimpleTimingPort(_name, _tester), tester(_tester), idx(_idx) {} - uint idx; + uint32_t idx; protected: virtual bool recvTiming(PacketPtr pkt); diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 43e140178..4cf9aed1c 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -89,7 +89,7 @@ SeriesRequestGenerator::initiate() } void -SeriesRequestGenerator::performCallback(uint proc, Addr address) +SeriesRequestGenerator::performCallback(uint32_t proc, Addr address) { assert(m_active_node == proc); assert(m_address == address); diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh index 97b632a12..9b1c3e8ba 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.hh +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.hh @@ -49,13 +49,13 @@ class SeriesRequestGenerator : public DirectedGenerator ~SeriesRequestGenerator(); bool initiate(); - void performCallback(uint proc, Addr address); + void performCallback(uint32_t proc, Addr address); private: SeriesRequestGeneratorStatus m_status; Addr m_address; - uint m_active_node; - uint m_addr_increment_size; + uint32_t m_active_node; + uint32_t m_addr_increment_size; bool m_issue_writes; }; -- cgit v1.2.3 From d2c26f402cfdb9a7fd34e98e3fc7aaa48c56c99b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 9 Jan 2012 18:08:20 -0600 Subject: O3: Add support of function tracing with O3 CPU. --- src/cpu/base.hh | 9 ++++----- src/cpu/o3/commit_impl.hh | 3 +++ 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/base.hh b/src/cpu/base.hh index ce02889f3..638556deb 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -291,17 +291,16 @@ class BaseCPU : public MemObject void enableFunctionTrace(); void traceFunctionsInternal(Addr pc); - protected: + private: + static std::vector cpuList; //!< Static global cpu list + + public: void traceFunctions(Addr pc) { if (functionTracingEnabled) traceFunctionsInternal(pc); } - private: - static std::vector cpuList; //!< Static global cpu list - - public: static int numSimulatedCPUs() { return cpuList.size(); } static Counter numSimulatedInstructions() { diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 75ae87c75..9ff31a622 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -52,6 +52,7 @@ #include "config/use_checker.hh" #include "cpu/o3/commit.hh" #include "cpu/o3/thread_state.hh" +#include "cpu/base.hh" #include "cpu/exetrace.hh" #include "cpu/timebuf.hh" #include "debug/Activity.hh" @@ -992,6 +993,8 @@ DefaultCommit::commitInsts() // Updates misc. registers. head_inst->updateMiscRegs(); + cpu->traceFunctions(pc[tid].instAddr()); + TheISA::advancePC(pc[tid], head_inst->staticInst); // Keep track of the last sequence number commited -- cgit v1.2.3 From 525d1e46dcb3180c8d73996adc025ce255575bd7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 9 Jan 2012 18:08:20 -0600 Subject: O3: Remove some asserts that no longer seem to be valid. --- src/cpu/o3/decode_impl.hh | 4 ---- src/cpu/o3/rename_impl.hh | 4 ---- 2 files changed, 8 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 0c0ec768e..a523a8b45 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -447,10 +447,6 @@ void DefaultDecode::sortInsts() { int insts_from_fetch = fromFetch->size; -#ifdef DEBUG - for (ThreadID tid = 0; tid < numThreads; tid++) - assert(insts[tid].empty()); -#endif for (int i = 0; i < insts_from_fetch; ++i) { insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]); } diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index fc93a5197..98c0f231b 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -767,10 +767,6 @@ void DefaultRename::sortInsts() { int insts_from_decode = fromDecode->size; -#ifdef DEBUG - for (ThreadID tid = 0; tid < numThreads; tid++) - assert(insts[tid].empty()); -#endif for (int i = 0; i < insts_from_decode; ++i) { DynInstPtr inst = fromDecode->insts[i]; insts[inst->threadNumber].push_back(inst); -- cgit v1.2.3 From b587d511c3819576ce1195b59416083cbd42522a Mon Sep 17 00:00:00 2001 From: Anders Handler Date: Mon, 9 Jan 2012 20:05:07 -0500 Subject: CPU: Remove Alpha-specific PC alignment check. --- src/cpu/pc_event.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index f9955d014..385a83b27 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -84,7 +84,9 @@ PCEventQueue::schedule(PCEvent *event) bool PCEventQueue::doService(ThreadContext *tc) { - Addr pc = tc->instAddr() & ~0x3; + // This will fail to break on Alpha PALcode addresses, but that is + // a rare use case. + Addr pc = tc->instAddr(); int serviced = 0; range_t range = equal_range(pc); for (iterator i = range.first; i != range.second; ++i) { @@ -92,7 +94,7 @@ PCEventQueue::doService(ThreadContext *tc) // another event. This for example, prevents two invocations // of the SkipFuncEvent. Maybe we should have separate PC // event queues for each processor? - if (pc != (tc->instAddr() & ~0x3)) + if (pc != tc->instAddr()) continue; DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n", -- cgit v1.2.3 From 9957035a42653a0666e30c744ab02fb0074db3a3 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Tue, 10 Jan 2012 10:15:02 -0600 Subject: DPRINTF: Improve some dprintf messages. --- src/cpu/o3/iew_impl.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 9c4b1068d..92c8875e4 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1340,10 +1340,10 @@ DefaultIEW::executeInsts() fetchRedirect[tid] = true; DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); - DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", - inst->predInstAddr(), inst->predNextInstAddr()); + DPRINTF(IEW, "Predicted target was PC: %s.\n", + inst->readPredTarg()); DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", - inst->pcState(), inst->nextInstAddr()); + inst->pcState()); // If incorrect, then signal the ROB that it must be squashed. squashDueToBranch(inst, tid); -- cgit v1.2.3 From a7394ad6807bd5e85f680184bf308673ca00534a Mon Sep 17 00:00:00 2001 From: Maximilien Breughe Date: Thu, 12 Jan 2012 10:15:00 -0500 Subject: inorder: MDU deadlock fix --- src/cpu/inorder/resources/mult_div_unit.cc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu') diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc index 0ff05252c..ab0081787 100644 --- a/src/cpu/inorder/resources/mult_div_unit.cc +++ b/src/cpu/inorder/resources/mult_div_unit.cc @@ -299,6 +299,7 @@ MultDivUnit::exeMulDiv(int slot_num) } mult_div_req->setProcessing(false); + cpu->wakeCPU(); } void -- cgit v1.2.3