From df7730b6774a730d554bfaa469ad95eeeffd3dc9 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Wed, 20 Jun 2007 19:46:45 -0700
Subject: Fix compiler errors.

--HG--
extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
---
 src/cpu/base_dyn_inst.hh      |  8 ++++----
 src/cpu/base_dyn_inst_impl.hh |  6 +++---
 src/cpu/o3/fetch_impl.hh      | 23 +++++++++++------------
 3 files changed, 18 insertions(+), 19 deletions(-)

(limited to 'src/cpu')

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 1311e5cf2..a55c1e3c0 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -498,11 +498,11 @@ class BaseDynInst : public FastAlloc, public RefCounted
     bool isQuiesce() const { return staticInst->isQuiesce(); }
     bool isIprAccess() const { return staticInst->isIprAccess(); }
     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
-    bool isMacroOp() const { return staticInst->isMacroOp(); }
-    bool isMicroOp() const { return staticInst->isMicroOp(); }
+    bool isMacroop() const { return staticInst->isMacroop(); }
+    bool isMicroop() const { return staticInst->isMicroop(); }
     bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
-    bool isLastMicroOp() const { return staticInst->isLastMicroOp(); }
-    bool isFirstMicroOp() const { return staticInst->isFirstMicroOp(); }
+    bool isLastMicroop() const { return staticInst->isLastMicroop(); }
+    bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
     bool isMicroBranch() const { return staticInst->isMicroBranch(); }
 
     /** Temporarily sets this instruction as a serialize before instruction. */
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index acf8af9cf..5c18ae694 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -73,7 +73,7 @@ BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
     seqNum = seq_num;
 
     bool nextIsMicro =
-        staticInst->isMicroOp() && !staticInst->isLastMicroOp();
+        staticInst->isMicroop() && !staticInst->isLastMicroop();
 
     PC = inst_PC;
     microPC = inst_MicroPC;
@@ -101,12 +101,12 @@ BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
                                Addr pred_PC, Addr pred_NPC,
                                Addr pred_MicroPC,
                                InstSeqNum seq_num, ImplCPU *cpu)
-  : staticInst(inst), traceData(NULL), cpu(cpu)
+  : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
 {
     seqNum = seq_num;
 
     bool nextIsMicro =
-        staticInst->isMicroOp() && !staticInst->isLastMicroOp();
+        staticInst->isMicroop() && !staticInst->isLastMicroop();
 
     PC = inst_PC;
     microPC = inst_MicroPC;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0fd1e7bac..857a08629 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -498,7 +498,7 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
     bool predict_taken;
 
     if (!inst->isControl()) {
-        if (inst->isMicroOp() && !inst->isLastMicroOp()) {
+        if (inst->isMicroop() && !inst->isLastMicroop()) {
             next_MicroPC++;
         } else {
             next_PC  = next_NPC;
@@ -1120,14 +1120,14 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
 
                 ext_inst = predecoder.getExtMachInst();
-                staticInst = StaticInstPtr(ext_inst);
-                if (staticInst->isMacroOp())
+                staticInst = StaticInstPtr(ext_inst, fetch_PC);
+                if (staticInst->isMacroop())
                     macroop = staticInst;
             }
             do {
                 if (macroop) {
-                    staticInst = macroop->fetchMicroOp(fetch_MicroPC);
-                    if (staticInst->isLastMicroOp())
+                    staticInst = macroop->fetchMicroop(fetch_MicroPC);
+                    if (staticInst->isLastMicroop())
                         macroop = NULL;
                 }
 
@@ -1194,8 +1194,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 }
 
                 ++numInst;
-            } while (staticInst->isMicroOp() &&
-                     !staticInst->isLastMicroOp() &&
+            } while (staticInst->isMicroop() &&
+                     !staticInst->isLastMicroop() &&
                      numInst < fetchWidth);
             offset += instSize;
         }
@@ -1240,13 +1240,12 @@ DefaultFetch<Impl>::fetch(bool &status_change)
         // We will use a nop in order to carry the fault.
         ext_inst = TheISA::NoopMachInst;
 
-        StaticInstPtr staticInst = new StaticInst(ext_inst);
         // Create a new DynInst from the dummy nop.
-        DynInstPtr instruction = new DynInst(staticInst,
-                                             fetch_PC, fetch_NPC,
-                                             next_PC, next_NPC,
+        DynInstPtr instruction = new DynInst(ext_inst,
+                                             fetch_PC, fetch_NPC, fetch_MicroPC,
+                                             next_PC, next_NPC, next_MicroPC,
                                              inst_seq, cpu);
-        instruction->setPredTarg(next_PC, next_NPC);
+        instruction->setPredTarg(next_PC, next_NPC, 1);
         instruction->setTid(tid);
 
         instruction->setASID(tid);
-- 
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