From f338d60930e973d330d13715b8617c22b980dcca Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 9 Oct 2011 00:15:50 -0700 Subject: SE/FS: Build the Interrupt objects in SE mode. --- src/cpu/BaseCPU.py | 47 +++++++++++++++++------------------------------ src/cpu/base.cc | 15 ++++----------- src/cpu/base.hh | 14 +++++--------- 3 files changed, 26 insertions(+), 50 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index bf7577cc7..6640f3cea 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -43,28 +43,22 @@ default_tracer = ExeTracer() if buildEnv['TARGET_ISA'] == 'alpha': from AlphaTLB import AlphaDTB, AlphaITB - if buildEnv['FULL_SYSTEM']: - from AlphaInterrupts import AlphaInterrupts + from AlphaInterrupts import AlphaInterrupts elif buildEnv['TARGET_ISA'] == 'sparc': from SparcTLB import SparcTLB - if buildEnv['FULL_SYSTEM']: - from SparcInterrupts import SparcInterrupts + from SparcInterrupts import SparcInterrupts elif buildEnv['TARGET_ISA'] == 'x86': from X86TLB import X86TLB - if buildEnv['FULL_SYSTEM']: - from X86LocalApic import X86LocalApic + from X86LocalApic import X86LocalApic elif buildEnv['TARGET_ISA'] == 'mips': from MipsTLB import MipsTLB - if buildEnv['FULL_SYSTEM']: - from MipsInterrupts import MipsInterrupts + from MipsInterrupts import MipsInterrupts elif buildEnv['TARGET_ISA'] == 'arm': from ArmTLB import ArmTLB - if buildEnv['FULL_SYSTEM']: - from ArmInterrupts import ArmInterrupts + from ArmInterrupts import ArmInterrupts elif buildEnv['TARGET_ISA'] == 'power': from PowerTLB import PowerTLB - if buildEnv['FULL_SYSTEM']: - from PowerInterrupts import PowerInterrupts + from PowerInterrupts import PowerInterrupts class BaseCPU(MemObject): type = 'BaseCPU' @@ -93,41 +87,34 @@ class BaseCPU(MemObject): if buildEnv['TARGET_ISA'] == 'sparc': dtb = Param.SparcTLB(SparcTLB(), "Data TLB") itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.SparcInterrupts( + interrupts = Param.SparcInterrupts( SparcInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'alpha': dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.AlphaInterrupts( + interrupts = Param.AlphaInterrupts( AlphaInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - _localApic = X86LocalApic(pio_addr=0x2000000000000000) - interrupts = \ - Param.X86LocalApic(_localApic, "Interrupt Controller") + _localApic = X86LocalApic(pio_addr=0x2000000000000000) + interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'mips': dtb = Param.MipsTLB(MipsTLB(), "Data TLB") itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.MipsInterrupts( - MipsInterrupts(), "Interrupt Controller") + interrupts = Param.MipsInterrupts( + MipsInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'arm': dtb = Param.ArmTLB(ArmTLB(), "Data TLB") itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.ArmInterrupts( - ArmInterrupts(), "Interrupt Controller") + interrupts = Param.ArmInterrupts( + ArmInterrupts(), "Interrupt Controller") elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.PowerTLB(PowerTLB(), "Data TLB") itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") - if buildEnv['FULL_SYSTEM']: - interrupts = Param.PowerInterrupts( - PowerInterrupts(), "Interrupt Controller") + interrupts = Param.PowerInterrupts( + PowerInterrupts(), "Interrupt Controller") else: print "Don't know what TLB to use for ISA %s" % \ buildEnv['TARGET_ISA'] @@ -157,7 +144,7 @@ class BaseCPU(MemObject): _cached_ports = ["itb.walker.port", "dtb.walker.port"] _uncached_ports = [] - if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: + if buildEnv['TARGET_ISA'] == 'x86': _uncached_ports = ["interrupts.pio", "interrupts.int_port"] def connectCachedPorts(self, bus): diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 1e25a5982..d5343aa64 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -100,18 +100,11 @@ CPUProgressEvent::description() const return "CPU Progress"; } -#if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), interrupts(p->interrupts), numThreads(p->numThreads), system(p->system), phase(p->phase) -#else -BaseCPU::BaseCPU(Params *p) - : MemObject(p), clock(p->clock), _cpuId(p->cpu_id), - numThreads(p->numThreads), system(p->system), - phase(p->phase) -#endif { // currentTick = curTick(); @@ -202,9 +195,9 @@ BaseCPU::BaseCPU(Params *p) schedule(event, p->function_trace_start); } } -#if FULL_SYSTEM interrupts->setCPU(this); +#if FULL_SYSTEM profileEvent = NULL; if (params()->profile) profileEvent = new ProfileEvent(this, params()->profile); @@ -395,10 +388,10 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc) } } -#if FULL_SYSTEM interrupts = oldCPU->interrupts; interrupts->setCPU(this); +#if FULL_SYSTEM for (ThreadID i = 0; i < size; ++i) threadContexts[i]->profileClear(); @@ -440,6 +433,8 @@ BaseCPU::ProfileEvent::process() cpu->schedule(this, curTick() + interval); } +#endif // FULL_SYSTEM + void BaseCPU::serialize(std::ostream &os) { @@ -454,8 +449,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string §ion) interrupts->unserialize(cp, section); } -#endif // FULL_SYSTEM - void BaseCPU::traceFunctionsInternal(Addr pc) { diff --git a/src/cpu/base.hh b/src/cpu/base.hh index ce02889f3..9c75539b1 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -36,6 +36,7 @@ #include +#include "arch/interrupts.hh" #include "arch/isa_traits.hh" #include "arch/microcode_rom.hh" #include "base/statistics.hh" @@ -45,10 +46,6 @@ #include "sim/eventq.hh" #include "sim/insttracer.hh" -#if FULL_SYSTEM -#include "arch/interrupts.hh" -#endif - class BaseCPUParams; class BranchPred; class CheckerCPU; @@ -125,7 +122,6 @@ class BaseCPU : public MemObject TheISA::MicrocodeRom microcodeRom; -#if FULL_SYSTEM protected: TheISA::Interrupts *interrupts; @@ -136,13 +132,17 @@ class BaseCPU : public MemObject return interrupts; } +#if FULL_SYSTEM virtual void wakeup() = 0; +#endif void postInterrupt(int int_num, int index) { interrupts->post(int_num, index); +#if FULL_SYSTEM wakeup(); +#endif } void @@ -174,7 +174,6 @@ class BaseCPU : public MemObject void process(); }; ProfileEvent *profileEvent; -#endif protected: std::vector threadContexts; @@ -257,7 +256,6 @@ class BaseCPU : public MemObject Tick phase; -#if FULL_SYSTEM /** * Serialize this object to the given output stream. * @param os The stream to serialize to. @@ -271,8 +269,6 @@ class BaseCPU : public MemObject */ virtual void unserialize(Checkpoint *cp, const std::string §ion); -#endif - /** * Return pointer to CPU's branch predictor (NULL if none). * @return Branch predictor pointer. -- cgit v1.2.3