From ff88f3b13ab03b1d6e8f371298843cd3b4d0b8cb Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 27 Dec 2006 14:35:23 -0500 Subject: Compare legion and m5 tlbs for differences Only print faults instructions that aren't traps or faulting loads src/cpu/exetrace.cc: Compare the legion and m5 tlbs and printout any differences Only show differences if the instruction isn't a trap and isn't a memory operation that changes the trap level (a fault) src/cpu/m5legion_interface.h: update the m5<->legion interface to add tlb data --HG-- extra : convert_revision : 6963b64ca1012604e6b1d3c5e0e5f5282fd0164e --- src/cpu/exetrace.cc | 34 ++++++++++++++++++++++++++++++---- src/cpu/m5legion_interface.h | 5 ++++- 2 files changed, 34 insertions(+), 5 deletions(-) (limited to 'src/cpu') diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index dc76ae189..352a11958 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -312,6 +312,7 @@ Trace::InstRecord::dump(ostream &outs) bool diffCanrestore = false; bool diffOtherwin = false; bool diffCleanwin = false; + bool diffTlb = false; Addr m5Pc, lgnPc; @@ -395,16 +396,23 @@ Trace::InstRecord::dump(ostream &outs) if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN)) diffCleanwin = true; + for (int i = 0; i < 64; i++) { + if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i)) + diffTlb = true; + if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i)) + diffTlb = true; + } + if ((diffPC || diffCC || diffInst || diffRegs || diffTpc || diffTnpc || diffTstate || diffTt || diffHpstate || diffHtstate || diffHtba || diffPstate || diffY || diffCcr || diffTl || diffGl || diffAsi || diffPil || diffCwp || diffCansave || diffCanrestore || - diffOtherwin || diffCleanwin) + diffOtherwin || diffCleanwin || diffTlb) && !((staticInst->machInst & 0xC1F80000) == 0x81D00000) - && !((staticInst->machInst & 0xC1F80000) == 0xC0580000) - && !((staticInst->machInst & 0xC1F80000) == 0xC0000000) - && !((staticInst->machInst & 0xC1F80000) == 0xC0700000)) { + && !(((staticInst->machInst & 0xC0000000) == 0xC0000000) + && shared_data->tl == thread->readMiscReg(MISCREG_TL) + 1) + ) { outs << "Differences found between M5 and Legion:"; if (diffPC) @@ -453,6 +461,8 @@ Trace::InstRecord::dump(ostream &outs) outs << " [Otherwin]"; if (diffCleanwin) outs << " [Cleanwin]"; + if (diffTlb) + outs << " [Tlb]"; outs << endl << endl; outs << right << setfill(' ') << setw(15) @@ -577,6 +587,22 @@ Trace::InstRecord::dump(ostream &outs) << endl;*/ } } + printColumnLabels(outs); + char label[8]; + for (int x = 0; x < 64; x++) { + if (shared_data->itb[x] != ULL(0xFFFFFFFFFFFFFFFF) || + thread->getITBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { + sprintf(label, "I-TLB:%02d", x); + printRegPair(outs, label, thread->getITBPtr()->TteRead(x), shared_data->itb[x]); + } + } + for (int x = 0; x < 64; x++) { + if (shared_data->dtb[x] != ULL(0xFFFFFFFFFFFFFFFF) || + thread->getDTBPtr()->TteRead(x) != ULL(0xFFFFFFFFFFFFFFFF)) { + sprintf(label, "D-TLB:%02d", x); + printRegPair(outs, label, thread->getDTBPtr()->TteRead(x), shared_data->dtb[x]); + } + } thread->getITBPtr()->dumpAll(); thread->getDTBPtr()->dumpAll(); diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h index bfb88485a..c3ba5986e 100644 --- a/src/cpu/m5legion_interface.h +++ b/src/cpu/m5legion_interface.h @@ -30,7 +30,7 @@ #include -#define VERSION 0xA1000006 +#define VERSION 0xA1000007 #define OWN_M5 0x000000AA #define OWN_LEGION 0x00000055 @@ -72,6 +72,9 @@ typedef struct { uint8_t otherwin; uint8_t cleanwin; + uint64_t itb[64]; + uint64_t dtb[64]; + } SharedData; /** !!! ^^^ Increment VERSION on change ^^^ !!! **/ -- cgit v1.2.3