From abc212461b865a47437a8dbf532b497ea4562137 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 13 Feb 2012 06:46:43 -0500 Subject: MEM: Explicit ports and Python binding on CopyEngine The copy-engine ports were previously created implicitly and bound based on the dma port peer rather than relying on the normal Python binding (connectPorts) being called explicitly. This patch makes the copy engine port similar to all other ports in that they are visibly in the Python class and bound using the normal explicit calls through Python. --- src/dev/CopyEngine.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/dev/CopyEngine.py') diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py index 29d9a23dd..b89486be8 100644 --- a/src/dev/CopyEngine.py +++ b/src/dev/CopyEngine.py @@ -33,6 +33,7 @@ from Pci import PciDevice class CopyEngine(PciDevice): type = 'CopyEngine' + dma = VectorMasterPort("Copy engine DMA port") VendorID = 0x8086 DeviceID = 0x1a38 Revision = 0xA2 # CM2 stepping (newest listed) -- cgit v1.2.3