From 6248e12704275bf4cc88f1743bb3a4bff7adcf9f Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 13 Aug 2008 17:41:58 -0400 Subject: Add the ability to specify a think time before descriptor fetch/writeback starts/ends as well as after read/write dmas --- src/dev/Ethernet.py | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/dev/Ethernet.py') diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py index 2beb0d537..01384b32b 100644 --- a/src/dev/Ethernet.py +++ b/src/dev/Ethernet.py @@ -98,6 +98,13 @@ class IGbE(EtherDevice): InterruptLine = 0x1e InterruptPin = 0x01 BAR0Size = '128kB' + wb_delay = Param.Latency('10ns', "delay before desc writeback occurs") + fetch_delay = Param.Latency('10ns', "delay before desc fetch occurs") + fetch_comp_delay = Param.Latency('10ns', "delay after desc fetch occurs") + wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs") + tx_read_delay = Param.Latency('0ns', "delay after tx dma read") + rx_write_delay = Param.Latency('0ns', "delay after rx dma read") + class EtherDevBase(EtherDevice): type = 'EtherDevBase' -- cgit v1.2.3