From 5a9a743cfc4517f93e5c94533efa767b92272c59 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 13 Feb 2012 06:43:09 -0500 Subject: MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. --- src/dev/alpha/Tsunami.py | 50 ++++++++++++++++++++++++------------------------ 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'src/dev/alpha') diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py index e6a899604..9a3ec0593 100644 --- a/src/dev/alpha/Tsunami.py +++ b/src/dev/alpha/Tsunami.py @@ -93,30 +93,30 @@ class Tsunami(Platform): # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): - self.cchip.pio = bus.port - self.pchip.pio = bus.port + self.cchip.pio = bus.master + self.pchip.pio = bus.master self.pciconfig.pio = bus.default bus.use_default_range = True - self.fake_sm_chip.pio = bus.port - self.fake_uart1.pio = bus.port - self.fake_uart2.pio = bus.port - self.fake_uart3.pio = bus.port - self.fake_uart4.pio = bus.port - self.fake_ppc.pio = bus.port - self.fake_OROM.pio = bus.port - self.fake_pnp_addr.pio = bus.port - self.fake_pnp_write.pio = bus.port - self.fake_pnp_read0.pio = bus.port - self.fake_pnp_read1.pio = bus.port - self.fake_pnp_read2.pio = bus.port - self.fake_pnp_read3.pio = bus.port - self.fake_pnp_read4.pio = bus.port - self.fake_pnp_read5.pio = bus.port - self.fake_pnp_read6.pio = bus.port - self.fake_pnp_read7.pio = bus.port - self.fake_ata0.pio = bus.port - self.fake_ata1.pio = bus.port - self.fb.pio = bus.port - self.io.pio = bus.port - self.uart.pio = bus.port - self.backdoor.pio = bus.port + self.fake_sm_chip.pio = bus.master + self.fake_uart1.pio = bus.master + self.fake_uart2.pio = bus.master + self.fake_uart3.pio = bus.master + self.fake_uart4.pio = bus.master + self.fake_ppc.pio = bus.master + self.fake_OROM.pio = bus.master + self.fake_pnp_addr.pio = bus.master + self.fake_pnp_write.pio = bus.master + self.fake_pnp_read0.pio = bus.master + self.fake_pnp_read1.pio = bus.master + self.fake_pnp_read2.pio = bus.master + self.fake_pnp_read3.pio = bus.master + self.fake_pnp_read4.pio = bus.master + self.fake_pnp_read5.pio = bus.master + self.fake_pnp_read6.pio = bus.master + self.fake_pnp_read7.pio = bus.master + self.fake_ata0.pio = bus.master + self.fake_ata1.pio = bus.master + self.fb.pio = bus.master + self.io.pio = bus.master + self.uart.pio = bus.master + self.backdoor.pio = bus.master -- cgit v1.2.3