From 579443c64fd176ec2af4c7f38b3d37484ad21ffa Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 30 Aug 2018 16:43:02 +0100 Subject: dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini Reviewed-by: Andreas Sandberg Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg --- src/dev/arm/Gic.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/dev/arm/Gic.py') diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py index 5f756639e..4cc661f0b 100644 --- a/src/dev/arm/Gic.py +++ b/src/dev/arm/Gic.py @@ -52,6 +52,7 @@ class BaseGic(PioDevice): class ArmInterruptPin(SimObject): type = 'ArmInterruptPin' cxx_header = "dev/arm/base_gic.hh" + cxx_class = "ArmInterruptPinGen" abstract = True platform = Param.Platform(Parent.any, "Platform with interrupt controller") @@ -60,11 +61,12 @@ class ArmInterruptPin(SimObject): class ArmSPI(ArmInterruptPin): type = 'ArmSPI' cxx_header = "dev/arm/base_gic.hh" + cxx_class = "ArmSPIGen" class ArmPPI(ArmInterruptPin): type = 'ArmPPI' cxx_header = "dev/arm/base_gic.hh" - + cxx_class = "ArmPPIGen" class Pl390(BaseGic): type = 'Pl390' -- cgit v1.2.3