From 2f2f508c74b532ef4b9e083879a6c27b17e7bcb1 Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Thu, 24 Oct 2019 12:47:22 +0100 Subject: dev-arm: add Watchdog Module SP805 model This provides a model of the Arm Watchdog Module SP805. This is based on the public TRM rev. r1p0 (ARM DDI 0270B). Integration test harness is not supported. Auto-generation of device tree entries is provided. Change-Id: I6157cec2212d0a1d2685bcfa983d2acbae1f3377 Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24205 Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/dev/arm/RealView.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src/dev/arm/RealView.py') diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index e773096b7..73f654ddf 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -402,6 +402,34 @@ class Sp804(AmbaPioDevice): clock1 = Param.Clock('1MHz', "Clock speed of the input") amba_id = 0x00141804 +class Sp805(AmbaIntDevice): + """ +Arm Watchdog Module (SP805) +Reference: + Arm Watchdog Module (SP805) - Technical Reference Manual - rev. r1p0 + Doc. ID: ARM DDI 0270B + """ + + type = 'Sp805' + cxx_header = 'dev/arm/watchdog_sp805.hh' + + amba_id = 0x00141805 + + def generateDeviceTree(self, state): + node = self.generateBasicPioDeviceNode(state, 'watchdog', + self.pio_addr, 0x1000, [int(self.int_num)]) + node.appendCompatible(['arm,sp805', 'arm,primecell']) + clocks = [state.phandle(self.clk_domain.unproxy(self))] + clock_names = ['wdogclk'] + platform = self._parent.unproxy(self) + if self in platform._off_chip_devices(): + clocks.append(state.phandle(platform.dcc.osc_smb)) + clock_names.append('apb_pclk') + node.append(FdtPropertyWords('clocks', clocks)) + node.append(FdtPropertyStrings('clock-names', clock_names)) + + yield node + class A9GlobalTimer(BasicPioDevice): type = 'A9GlobalTimer' cxx_header = "dev/arm/timer_a9global.hh" -- cgit v1.2.3