From 476fd104a80095207eec0b594baa642937fbac01 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Thu, 22 Mar 2018 17:58:59 +0000 Subject: dev, arm: Add misc reg tracing to the generic timer Change-Id: Ice9376b8eb42423679b0191910e8c980f8017f88 Signed-off-by: Andreas Sandberg Reviewed-by: Giacomo Travaglini Reviewed-by: Curtis Dunham Reviewed-on: https://gem5-review.googlesource.com/12398 --- src/dev/arm/generic_timer.hh | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) (limited to 'src/dev/arm/generic_timer.hh') diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh index 2c5776590..1c9449e05 100644 --- a/src/dev/arm/generic_timer.hh +++ b/src/dev/arm/generic_timer.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, 2015, 2017 ARM Limited + * Copyright (c) 2013, 2015, 2017-2018 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -318,12 +318,8 @@ class GenericTimerISA : public ArmISA::BaseISADevice GenericTimerISA(GenericTimer &_parent, unsigned _cpu) : parent(_parent), cpu(_cpu) {} - void setMiscReg(int misc_reg, ArmISA::MiscReg val) override { - parent.setMiscReg(misc_reg, cpu, val); - } - ArmISA::MiscReg readMiscReg(int misc_reg) override { - return parent.readMiscReg(misc_reg, cpu); - } + void setMiscReg(int misc_reg, ArmISA::MiscReg val) override; + ArmISA::MiscReg readMiscReg(int misc_reg) override; protected: GenericTimer &parent; -- cgit v1.2.3