From af1838be8d1efbbbb7133262f23f9f757033589d Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 22 Jul 2019 17:38:29 +0100
Subject: dev-arm: Define enum masks for SMMU_CR0 register

The configuration register is a vital register in the SMMU, and using
enum masks will make the code more readable/understandable

Change-Id: Ia117db56c457fe876ae38be391c386e502f34384
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19632
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/dev/arm/smmu_v3_defs.hh | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'src/dev/arm/smmu_v3_defs.hh')

diff --git a/src/dev/arm/smmu_v3_defs.hh b/src/dev/arm/smmu_v3_defs.hh
index 991e90c7b..d993fd715 100644
--- a/src/dev/arm/smmu_v3_defs.hh
+++ b/src/dev/arm/smmu_v3_defs.hh
@@ -311,6 +311,15 @@ struct ContextDescriptor
     uint64_t _pad[3];
 };
 
+enum {
+    CR0_SMMUEN_MASK = 0x1,
+    CR0_PRIQEN_MASK = 0x2,
+    CR0_EVENTQEN_MASK = 0x4,
+    CR0_CMDQEN_MASK = 0x8,
+    CR0_ATSCHK_MASK = 0x10,
+    CR0_VMW_MASK = 0x1C0,
+};
+
 enum SMMUCommandType {
     CMD_PRF_CONFIG   = 0x1000,
     CMD_PRF_ADDR     = 0x1001,
-- 
cgit v1.2.3