From 1470dae8e949eaef8232dc621d9074329357265c Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Tue, 17 Nov 2009 18:02:08 -0600
Subject: ARM: Boilerplate full-system code.

--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
---
 src/dev/arm/versatile.cc | 122 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 122 insertions(+)
 create mode 100644 src/dev/arm/versatile.cc

(limited to 'src/dev/arm/versatile.cc')

diff --git a/src/dev/arm/versatile.cc b/src/dev/arm/versatile.cc
new file mode 100644
index 000000000..7d571db99
--- /dev/null
+++ b/src/dev/arm/versatile.cc
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2009 ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of Versatile platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "config/the_isa.hh"
+#include "cpu/intr_control.hh"
+#include "dev/arm/versatile.hh"
+#include "dev/terminal.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace TheISA;
+
+Versatile::Versatile(const Params *p)
+    : Platform(p), system(p->system)
+{
+    // set the back pointer from the system to myself
+    system->platform = this;
+}
+
+Tick
+Versatile::intrFrequency()
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+void
+Versatile::postConsoleInt()
+{
+    warn_once("Don't know what interrupt to post for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+Versatile::clearConsoleInt()
+{
+    warn_once("Don't know what interrupt to clear for console.\n");
+    //panic("Need implementation\n");
+}
+
+void
+Versatile::postPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+void
+Versatile::clearPciInt(int line)
+{
+    panic("Need implementation\n");
+}
+
+Addr
+Versatile::pciToDma(Addr pciAddr) const
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+
+Addr
+Versatile::calcPciConfigAddr(int bus, int dev, int func)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+Versatile::calcPciIOAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Addr
+Versatile::calcPciMemAddr(Addr addr)
+{
+    panic("Need implementation\n");
+    M5_DUMMY_RETURN
+}
+
+Versatile *
+VersatileParams::create()
+{
+    return new Versatile(this);
+}
-- 
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