From 6cf9f182f678e4ddf2a2b98a5093a7418353217c Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 14 Feb 2012 14:15:30 -0500 Subject: MEM: Fix residual bus ports and make them master/slave This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level. --- src/dev/arm/RealView.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/dev/arm') diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py index e42bc4b94..48a7cf316 100644 --- a/src/dev/arm/RealView.py +++ b/src/dev/arm/RealView.py @@ -376,7 +376,7 @@ class VExpress_ELT(RealView): self.elba_kmi1.pio = bus.master self.cf_ctrl.pio = bus.master self.cf_ctrl.config = bus.master - self.cf_ctrl.dma = bus.port + self.cf_ctrl.dma = bus.slave self.ide.pio = bus.master self.ide.config = bus.master self.ide.dma = bus.slave -- cgit v1.2.3