From a17afb1649e26c248dc4a61e4a0ef6671785e992 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Fri, 13 Oct 2006 15:47:05 -0400 Subject: Fix for DMA's in FS caches. Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd --- src/dev/io_device.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/dev/io_device.hh') diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index df4f494cb..24e822a40 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -256,7 +256,7 @@ class DmaDevice : public PioDevice virtual ~DmaDevice(); void dmaWrite(Addr addr, int size, Event *event, uint8_t *data) - { dmaPort->dmaAction(Packet::WriteReq, addr, size, event, data) ; } + { dmaPort->dmaAction(Packet::WriteInvalidateReq, addr, size, event, data) ; } void dmaRead(Addr addr, int size, Event *event, uint8_t *data = NULL) { dmaPort->dmaAction(Packet::ReadReq, addr, size, event, data); } -- cgit v1.2.3