From 6cf9f182f678e4ddf2a2b98a5093a7418353217c Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Tue, 14 Feb 2012 14:15:30 -0500 Subject: MEM: Fix residual bus ports and make them master/slave This patch cleans up a number of remaining uses of bus.port which is now split into bus.master and bus.slave. The only non-trivial change is the memtest where the level building now has to be aware of the role of the ports used in the previous level. --- src/dev/mips/Malta.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/dev/mips') diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py index ddde06687..23a5e5c8f 100755 --- a/src/dev/mips/Malta.py +++ b/src/dev/mips/Malta.py @@ -63,6 +63,6 @@ class Malta(Platform): # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): - self.cchip.pio = bus.port - self.io.pio = bus.port - self.uart.pio = bus.port + self.cchip.pio = bus.master + self.io.pio = bus.master + self.uart.pio = bus.master -- cgit v1.2.3