From 17b0e9714d4bde7462d4663899bb9498027f6b40 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 18 Sep 2006 20:12:45 -0400 Subject: add boiler plate intel nic code src/SConscript: add intel nic to sconscript src/dev/pcidev.cc: fix bug with subsystemid value src/python/m5/objects/Ethernet.py: add intel nic to ethernet.py src/python/m5/objects/Ide.py: src/python/m5/objects/Pci.py: Move config_latency into pci where it belogs --HG-- extra : convert_revision : 7163aaf7b4098496518b0910cef62f2ce3dd574d --- src/dev/pcidev.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/dev/pcidev.cc') diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index 8ea22cb24..c3b83f448 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -405,7 +405,7 @@ CREATE_SIM_OBJECT(PciConfigData) data->config.baseAddr[5] = htole(BAR5); data->config.cardbusCIS = htole(CardbusCIS); data->config.subsystemVendorID = htole(SubsystemVendorID); - data->config.subsystemID = htole(SubsystemVendorID); + data->config.subsystemID = htole(SubsystemID); data->config.expansionROM = htole(ExpansionROM); data->config.interruptLine = htole(InterruptLine); data->config.interruptPin = htole(InterruptPin); -- cgit v1.2.3