From 6b70afd0d4ec8821105e506d7a20f9af01b8eafb Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 6 Nov 2015 03:26:36 -0500 Subject: mem: Use the packet delays and do not just zero them out This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address. --- src/dev/pcidev.cc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'src/dev/pcidev.cc') diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index 4126141b9..7b542ab1c 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013 ARM Limited + * Copyright (c) 2013, 2015 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -79,9 +79,15 @@ PciDevice::PciConfigPort::recvAtomic(PacketPtr pkt) { assert(pkt->getAddr() >= configAddr && pkt->getAddr() < configAddr + PCI_CONFIG_SIZE); - // @todo someone should pay for this + + // technically the packet only reaches us after the header delay, + // and typically we also need to deserialise any payload + Tick receive_delay = pkt->headerDelay + pkt->payloadDelay; pkt->headerDelay = pkt->payloadDelay = 0; - return pkt->isRead() ? device->readConfig(pkt) : device->writeConfig(pkt); + + const Tick delay(pkt->isRead() ? device->readConfig(pkt) : + device->writeConfig(pkt)); + return delay + receive_delay; } AddrRangeList -- cgit v1.2.3