From 139519ef87ceb4ab6c7f0246dd98b002e7bde3f9 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Tue, 12 Dec 2006 17:55:27 -0500 Subject: Fix bugs in tlbmap (and thus rangemap since the code is nearly identical) Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add a magic miscreg which reads all the bits the tlb needs in one go src/arch/sparc/tlb.cc: initialized the context type and id to reasonable values and handle block init stores src/arch/sparc/tlb_map.hh: fix bug in tlb map code src/base/range_map.hh: fix bug in rangemap code and add range_multimap (these are probably useful for bus range stuff) src/cpu/exetrace.cc: fixup tcc ignore code to be correct src/dev/sparc/t1000.cc: make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out src/unittest/rangemaptest.cc: fix up the rangemap unit test to catch the missing case --HG-- extra : convert_revision : 70604a8b5d0553aa0b0bd7649f775a0cfa8267a5 --- src/dev/sparc/t1000.cc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/dev/sparc/t1000.cc') diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc index 5fc787084..4a8de77a5 100644 --- a/src/dev/sparc/t1000.cc +++ b/src/dev/sparc/t1000.cc @@ -62,13 +62,15 @@ T1000::intrFrequency() void T1000::postConsoleInt() { - panic("Need implementation\n"); + warn_once("Don't know what interrupt to post for console.\n"); + //panic("Need implementation\n"); } void T1000::clearConsoleInt() { - panic("Need implementation\n"); + warn_once("Don't know what interrupt to clear for console.\n"); + //panic("Need implementation\n"); } void -- cgit v1.2.3