From 6cf9f182f678e4ddf2a2b98a5093a7418353217c Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 14 Feb 2012 14:15:30 -0500
Subject: MEM: Fix residual bus ports and make them master/slave

This patch cleans up a number of remaining uses of bus.port which
is now split into bus.master and bus.slave. The only non-trivial change
is the memtest where the level building now has to be aware of the role
of the ports used in the previous level.
---
 src/dev/sparc/T1000.py | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'src/dev/sparc')

diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index 901304251..aa66a9004 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -109,8 +109,8 @@ class T1000(Platform):
     iob = Iob()
     # Attach I/O devices that are on chip
     def attachOnChipIO(self, bus):
-        self.iob.pio = bus.port
-        self.htod.pio = bus.port
+        self.iob.pio = bus.master
+        self.htod.pio = bus.master
 
 
     # Attach I/O devices to specified bus object.  Can't do this
@@ -119,17 +119,17 @@ class T1000(Platform):
     def attachIO(self, bus):
         self.hvuart.terminal = self.hterm
         self.puart0.terminal = self.pterm
-        self.fake_clk.pio = bus.port
-        self.fake_membnks.pio = bus.port
-        self.fake_l2_1.pio = bus.port
-        self.fake_l2_2.pio = bus.port
-        self.fake_l2_3.pio = bus.port
-        self.fake_l2_4.pio = bus.port
-        self.fake_l2esr_1.pio = bus.port
-        self.fake_l2esr_2.pio = bus.port
-        self.fake_l2esr_3.pio = bus.port
-        self.fake_l2esr_4.pio = bus.port
-        self.fake_ssi.pio = bus.port
-        self.fake_jbi.pio = bus.port
-        self.puart0.pio = bus.port
-        self.hvuart.pio = bus.port
+        self.fake_clk.pio = bus.master
+        self.fake_membnks.pio = bus.master
+        self.fake_l2_1.pio = bus.master
+        self.fake_l2_2.pio = bus.master
+        self.fake_l2_3.pio = bus.master
+        self.fake_l2_4.pio = bus.master
+        self.fake_l2esr_1.pio = bus.master
+        self.fake_l2esr_2.pio = bus.master
+        self.fake_l2esr_3.pio = bus.master
+        self.fake_l2esr_4.pio = bus.master
+        self.fake_ssi.pio = bus.master
+        self.fake_jbi.pio = bus.master
+        self.puart0.pio = bus.master
+        self.hvuart.pio = bus.master
-- 
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