From 70cd5bfce5549495c6e969fa509bfd5f56190e10 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 1 Feb 2009 00:26:10 -0800
Subject: X86: Configure the first PCI interrupt.

---
 src/dev/x86/SouthBridge.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/dev/x86/SouthBridge.py')

diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 8d766471e..d89ed9dc6 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -87,7 +87,8 @@ class SouthBridge(SimObject):
     ide.BAR3LegacyIO = True
     ide.BAR4 = 1
     ide.Command = 1
-    ide.InterruptLine = 20
+    ide.InterruptLine = 14
+    ide.InterruptPin = 1
 
     def attachIO(self, bus):
         # Route interupt signals
-- 
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