From 826621eb1722eb557d4c24f79e110fbed09e5fb5 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Oct 2008 02:21:44 -0700 Subject: X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory. --HG-- rename : src/dev/x86/south_bridge/SouthBridge.py => src/dev/x86/SouthBridge.py rename : src/dev/x86/south_bridge/south_bridge.cc => src/dev/x86/south_bridge.cc rename : src/dev/x86/south_bridge/south_bridge.hh => src/dev/x86/south_bridge.hh --- src/dev/x86/SouthBridge.py | 69 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 src/dev/x86/SouthBridge.py (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py new file mode 100644 index 000000000..2f4b8438a --- /dev/null +++ b/src/dev/x86/SouthBridge.py @@ -0,0 +1,69 @@ +# Copyright (c) 2008 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * +from Cmos import Cmos +from I8254 import I8254 +from I8259 import I8259 +from PcSpeaker import PcSpeaker +from m5.SimObject import SimObject + +def x86IOAddress(port): + IO_address_space_base = 0x8000000000000000 + return IO_address_space_base + port; + +class SouthBridge(SimObject): + type = 'SouthBridge' + pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") + platform = Param.Platform(Parent.any, "Platform this device is part of") + + _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') + _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') + _cmos = Cmos(pio_addr=x86IOAddress(0x70)) + _pit = I8254(pio_addr=x86IOAddress(0x40)) + _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) + + pic1 = Param.I8259(_pic1, "Master PIC") + pic2 = Param.I8259(_pic2, "Slave PIC") + cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") + pit = Param.I8254(_pit, "Programmable interval timer") + speaker = Param.PcSpeaker(_speaker, "PC speaker") + + def attachIO(self, bus): + # Make internal connections + self.pic2.output = self.pic1.pin(2) + self.cmos.int_pin = self.pic2.pin(0) + self.pit.int_pin = self.pic1.pin(0) + self.speaker.i8254 = self.pit + # Connect to the bus + self.cmos.pio = bus.port + self.pic1.pio = bus.port + self.pic2.pio = bus.port + self.pit.pio = bus.port + self.speaker.pio = bus.port -- cgit v1.2.3 From 168e524b9bfc9a53465562e2901c65ef388a237b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Oct 2008 16:08:14 -0700 Subject: X86: Create an IO APIC device. --- src/dev/x86/SouthBridge.py | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 2f4b8438a..15ffe153f 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -29,6 +29,7 @@ from m5.params import * from m5.proxy import * from Cmos import Cmos +from I82094AA import I82094AA from I8254 import I8254 from I8259 import I8259 from PcSpeaker import PcSpeaker @@ -48,15 +49,18 @@ class SouthBridge(SimObject): _cmos = Cmos(pio_addr=x86IOAddress(0x70)) _pit = I8254(pio_addr=x86IOAddress(0x40)) _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) + _io_apic = I82094AA(pio_addr=0xFEC00000) pic1 = Param.I8259(_pic1, "Master PIC") pic2 = Param.I8259(_pic2, "Slave PIC") cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") pit = Param.I8254(_pit, "Programmable interval timer") speaker = Param.PcSpeaker(_speaker, "PC speaker") + io_apic = Param.I82094AA(_io_apic, "I/O APIC") def attachIO(self, bus): # Make internal connections + self.pic1.output = self.io_apic.pin(0) self.pic2.output = self.pic1.pin(2) self.cmos.int_pin = self.pic2.pin(0) self.pit.int_pin = self.pic1.pin(0) @@ -67,3 +71,4 @@ class SouthBridge(SimObject): self.pic2.pio = bus.port self.pit.pio = bus.port self.speaker.pio = bus.port + self.io_apic.pio = bus.port -- cgit v1.2.3 From 557bde43c331024eb5cecf4093a24a5b7a9cc266 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 12 Oct 2008 13:28:54 -0700 Subject: X86: Make APICs communicate through the memory system. --- src/dev/x86/SouthBridge.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 15ffe153f..8a9bea01b 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -72,3 +72,4 @@ class SouthBridge(SimObject): self.pit.pio = bus.port self.speaker.pio = bus.port self.io_apic.pio = bus.port + self.io_apic.int_port = bus.port -- cgit v1.2.3 From 56e182a6a9e58b951712582c4c63cf303847156e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 25 Jan 2009 20:35:00 -0800 Subject: X86: Add a dummy minimal DMA controller that doesn't do anything. --- src/dev/x86/SouthBridge.py | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 8a9bea01b..bbe3ad102 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -30,6 +30,7 @@ from m5.params import * from m5.proxy import * from Cmos import Cmos from I82094AA import I82094AA +from I8237 import I8237 from I8254 import I8254 from I8259 import I8259 from PcSpeaker import PcSpeaker @@ -47,6 +48,7 @@ class SouthBridge(SimObject): _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master') _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') _cmos = Cmos(pio_addr=x86IOAddress(0x70)) + _dma1 = I8237(pio_addr=x86IOAddress(0x0)) _pit = I8254(pio_addr=x86IOAddress(0x40)) _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) _io_apic = I82094AA(pio_addr=0xFEC00000) @@ -54,6 +56,7 @@ class SouthBridge(SimObject): pic1 = Param.I8259(_pic1, "Master PIC") pic2 = Param.I8259(_pic2, "Slave PIC") cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") + dma1 = Param.I8237(_dma1, "The first dma controller") pit = Param.I8254(_pit, "Programmable interval timer") speaker = Param.PcSpeaker(_speaker, "PC speaker") io_apic = Param.I82094AA(_io_apic, "I/O APIC") @@ -67,6 +70,7 @@ class SouthBridge(SimObject): self.speaker.i8254 = self.pit # Connect to the bus self.cmos.pio = bus.port + self.dma1.pio = bus.port self.pic1.pio = bus.port self.pic2.pio = bus.port self.pit.pio = bus.port -- cgit v1.2.3 From 6a3f255a84d93f3e621319fd81f355416e385c8c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 31 Jan 2009 23:33:54 -0800 Subject: X86: Rework interrupt pins to allow one to many connections. --- src/dev/x86/SouthBridge.py | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index bbe3ad102..ba9aaf2b4 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -34,6 +34,7 @@ from I8237 import I8237 from I8254 import I8254 from I8259 import I8259 from PcSpeaker import PcSpeaker +from X86IntPin import X86IntLine from m5.SimObject import SimObject def x86IOAddress(port): @@ -52,6 +53,9 @@ class SouthBridge(SimObject): _pit = I8254(pio_addr=x86IOAddress(0x40)) _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) _io_apic = I82094AA(pio_addr=0xFEC00000) + # This is to make sure the interrupt lines are instantiated. Don't use + # it for anything directly. + int_lines = VectorParam.X86IntLine([], "Interrupt lines") pic1 = Param.I8259(_pic1, "Master PIC") pic2 = Param.I8259(_pic2, "Slave PIC") @@ -61,13 +65,20 @@ class SouthBridge(SimObject): speaker = Param.PcSpeaker(_speaker, "PC speaker") io_apic = Param.I82094AA(_io_apic, "I/O APIC") + def connectPins(self, source, sink): + self.int_lines.append(X86IntLine(source=source, sink=sink)) + def attachIO(self, bus): - # Make internal connections - self.pic1.output = self.io_apic.pin(0) - self.pic2.output = self.pic1.pin(2) - self.cmos.int_pin = self.pic2.pin(0) - self.pit.int_pin = self.pic1.pin(0) + # Route interupt signals + self.connectPins(self.pic1.output, self.io_apic.pin(0)) + self.connectPins(self.pic2.output, self.pic1.pin(2)) + self.connectPins(self.cmos.int_pin, self.pic2.pin(0)) + self.connectPins(self.pit.int_pin, self.pic1.pin(0)) + self.connectPins(self.pit.int_pin, self.io_apic.pin(2)) + # Tell the devices about each other + self.pic1.slave = self.pic2 self.speaker.i8254 = self.pit + self.io_apic.external_int_pic = self.pic1 # Connect to the bus self.cmos.pio = bus.port self.dma1.pio = bus.port -- cgit v1.2.3 From 7cf276bed34c2ed1f8f86bbf46497aab3f8ebc6c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 31 Jan 2009 23:59:01 -0800 Subject: X86: Add a keyboard controller device. --- src/dev/x86/SouthBridge.py | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index ba9aaf2b4..a3db83610 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -29,6 +29,7 @@ from m5.params import * from m5.proxy import * from Cmos import Cmos +from I8042 import I8042 from I82094AA import I82094AA from I8237 import I8237 from I8254 import I8254 @@ -50,6 +51,8 @@ class SouthBridge(SimObject): _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave') _cmos = Cmos(pio_addr=x86IOAddress(0x70)) _dma1 = I8237(pio_addr=x86IOAddress(0x0)) + _keyboard = I8042(data_port=x86IOAddress(0x60), \ + command_port=x86IOAddress(0x64)) _pit = I8254(pio_addr=x86IOAddress(0x40)) _speaker = PcSpeaker(pio_addr=x86IOAddress(0x61)) _io_apic = I82094AA(pio_addr=0xFEC00000) @@ -61,6 +64,7 @@ class SouthBridge(SimObject): pic2 = Param.I8259(_pic2, "Slave PIC") cmos = Param.Cmos(_cmos, "CMOS memory and real time clock device") dma1 = Param.I8237(_dma1, "The first dma controller") + keyboard = Param.I8042(_keyboard, "The keyboard controller") pit = Param.I8254(_pit, "Programmable interval timer") speaker = Param.PcSpeaker(_speaker, "PC speaker") io_apic = Param.I82094AA(_io_apic, "I/O APIC") @@ -75,6 +79,14 @@ class SouthBridge(SimObject): self.connectPins(self.cmos.int_pin, self.pic2.pin(0)) self.connectPins(self.pit.int_pin, self.pic1.pin(0)) self.connectPins(self.pit.int_pin, self.io_apic.pin(2)) +# self.connectPins(self.keyboard.keyboard_int_pin, +# self.pic1.pin(1)) + self.connectPins(self.keyboard.keyboard_int_pin, + self.io_apic.pin(1)) +# self.connectPins(self.keyboard.mouse_int_pin, +# self.pic2.pin(4)) + self.connectPins(self.keyboard.mouse_int_pin, + self.io_apic.pin(12)) # Tell the devices about each other self.pic1.slave = self.pic2 self.speaker.i8254 = self.pit @@ -82,6 +94,7 @@ class SouthBridge(SimObject): # Connect to the bus self.cmos.pio = bus.port self.dma1.pio = bus.port + self.keyboard.pio = bus.port self.pic1.pio = bus.port self.pic2.pio = bus.port self.pit.pio = bus.port -- cgit v1.2.3 From bb7ad80bbe565800b09c38bdc02c12f827ec9240 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Feb 2009 00:00:03 -0800 Subject: X86: Plug in an IDE controller. --- src/dev/x86/SouthBridge.py | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index a3db83610..be9276145 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -34,6 +34,7 @@ from I82094AA import I82094AA from I8237 import I8237 from I8254 import I8254 from I8259 import I8259 +from Ide import IdeController from PcSpeaker import PcSpeaker from X86IntPin import X86IntLine from m5.SimObject import SimObject @@ -72,6 +73,21 @@ class SouthBridge(SimObject): def connectPins(self, source, sink): self.int_lines.append(X86IntLine(source=source, sink=sink)) + # IDE controller + ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0) + ide.BAR0 = 0x1f0 + ide.BAR0LegacyIO = True + ide.BAR1 = 0x3f4 + ide.BAR1Size = '3B' + ide.BAR1LegacyIO = True + ide.BAR2 = 0x170 + ide.BAR2LegacyIO = True + ide.BAR3 = 0x374 + ide.BAR3Size = '3B' + ide.BAR3LegacyIO = True + ide.BAR4 = 1 + ide.Command = 1 + def attachIO(self, bus): # Route interupt signals self.connectPins(self.pic1.output, self.io_apic.pin(0)) @@ -94,6 +110,7 @@ class SouthBridge(SimObject): # Connect to the bus self.cmos.pio = bus.port self.dma1.pio = bus.port + self.ide.pio = bus.port self.keyboard.pio = bus.port self.pic1.pio = bus.port self.pic2.pio = bus.port -- cgit v1.2.3 From f1b43b39a764645c8e15b66a1a01d404f03c8307 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Feb 2009 00:25:15 -0800 Subject: X86: Hook up the IDE controller interrupt line. --- src/dev/x86/SouthBridge.py | 1 + 1 file changed, 1 insertion(+) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index be9276145..8d766471e 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -87,6 +87,7 @@ class SouthBridge(SimObject): ide.BAR3LegacyIO = True ide.BAR4 = 1 ide.Command = 1 + ide.InterruptLine = 20 def attachIO(self, bus): # Route interupt signals -- cgit v1.2.3 From 70cd5bfce5549495c6e969fa509bfd5f56190e10 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 1 Feb 2009 00:26:10 -0800 Subject: X86: Configure the first PCI interrupt. --- src/dev/x86/SouthBridge.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/dev/x86/SouthBridge.py') diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 8d766471e..d89ed9dc6 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -87,7 +87,8 @@ class SouthBridge(SimObject): ide.BAR3LegacyIO = True ide.BAR4 = 1 ide.Command = 1 - ide.InterruptLine = 20 + ide.InterruptLine = 14 + ide.InterruptPin = 1 def attachIO(self, bus): # Route interupt signals -- cgit v1.2.3