From 3af428606ad35e2cd40d5d1d39010ff732bfee4f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Oct 2008 02:23:40 -0700 Subject: X86: Rename the PC device to Pc. --HG-- rename : src/dev/x86/PC.py => src/dev/x86/Pc.py --- src/dev/x86/PC.py | 71 --------------------------------------------- src/dev/x86/Pc.py | 71 +++++++++++++++++++++++++++++++++++++++++++++ src/dev/x86/SConscript | 2 +- src/dev/x86/pc.cc | 24 +++++++-------- src/dev/x86/pc.hh | 8 ++--- src/dev/x86/south_bridge.cc | 2 +- 6 files changed, 89 insertions(+), 89 deletions(-) delete mode 100644 src/dev/x86/PC.py create mode 100644 src/dev/x86/Pc.py (limited to 'src/dev/x86') diff --git a/src/dev/x86/PC.py b/src/dev/x86/PC.py deleted file mode 100644 index 28a722be9..000000000 --- a/src/dev/x86/PC.py +++ /dev/null @@ -1,71 +0,0 @@ -# Copyright (c) 2008 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -from m5.params import * -from m5.proxy import * - -from Device import IsaFake -from Pci import PciConfigAll -from Platform import Platform -from SouthBridge import SouthBridge -from Terminal import Terminal -from Uart import Uart8250 - -def x86IOAddress(port): - IO_address_space_base = 0x8000000000000000 - return IO_address_space_base + port; - -class PC(Platform): - type = 'PC' - system = Param.System(Parent.any, "system") - - pciconfig = PciConfigAll() - - south_bridge = SouthBridge() - - # "Non-existant" port used for timing purposes by the linux kernel - i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) - - # Ports behind the pci config and data regsiters. These don't do anything, - # but the linux kernel fiddles with them anway. - behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) - - # Serial port and terminal - terminal = Terminal() - com_1 = Uart8250() - com_1.pio_addr = x86IOAddress(0x3f8) - com_1.terminal = terminal - - def attachIO(self, bus): - self.south_bridge.attachIO(bus) - self.i_dont_exist.pio = bus.port - self.behind_pci.pio = bus.port - self.com_1.pio = bus.port - self.pciconfig.pio = bus.default - bus.responder_set = True - bus.responder = self.pciconfig diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py new file mode 100644 index 000000000..080844e4a --- /dev/null +++ b/src/dev/x86/Pc.py @@ -0,0 +1,71 @@ +# Copyright (c) 2008 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +from m5.params import * +from m5.proxy import * + +from Device import IsaFake +from Pci import PciConfigAll +from Platform import Platform +from SouthBridge import SouthBridge +from Terminal import Terminal +from Uart import Uart8250 + +def x86IOAddress(port): + IO_address_space_base = 0x8000000000000000 + return IO_address_space_base + port; + +class Pc(Platform): + type = 'Pc' + system = Param.System(Parent.any, "system") + + pciconfig = PciConfigAll() + + south_bridge = SouthBridge() + + # "Non-existant" port used for timing purposes by the linux kernel + i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) + + # Ports behind the pci config and data regsiters. These don't do anything, + # but the linux kernel fiddles with them anway. + behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) + + # Serial port and terminal + terminal = Terminal() + com_1 = Uart8250() + com_1.pio_addr = x86IOAddress(0x3f8) + com_1.terminal = terminal + + def attachIO(self, bus): + self.south_bridge.attachIO(bus) + self.i_dont_exist.pio = bus.port + self.behind_pci.pio = bus.port + self.com_1.pio = bus.port + self.pciconfig.pio = bus.default + bus.responder_set = True + bus.responder = self.pciconfig diff --git a/src/dev/x86/SConscript b/src/dev/x86/SConscript index b71649fdd..ae270aa90 100644 --- a/src/dev/x86/SConscript +++ b/src/dev/x86/SConscript @@ -31,7 +31,7 @@ Import('*') if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86': - SimObject('PC.py') + SimObject('Pc.py') Source('pc.cc') SimObject('SouthBridge.py') diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc index 7c35aebf2..0dc8d6cd5 100644 --- a/src/dev/x86/pc.cc +++ b/src/dev/x86/pc.cc @@ -47,7 +47,7 @@ using namespace std; using namespace TheISA; -PC::PC(const Params *p) +Pc::Pc(const Params *p) : Platform(p), system(p->system) { southBridge = NULL; @@ -56,7 +56,7 @@ PC::PC(const Params *p) } void -PC::init() +Pc::init() { assert(southBridge); I8254 & timer = *southBridge->pit; @@ -70,40 +70,40 @@ PC::init() } Tick -PC::intrFrequency() +Pc::intrFrequency() { panic("Need implementation\n"); M5_DUMMY_RETURN } void -PC::postConsoleInt() +Pc::postConsoleInt() { warn_once("Don't know what interrupt to post for console.\n"); //panic("Need implementation\n"); } void -PC::clearConsoleInt() +Pc::clearConsoleInt() { warn_once("Don't know what interrupt to clear for console.\n"); //panic("Need implementation\n"); } void -PC::postPciInt(int line) +Pc::postPciInt(int line) { panic("Need implementation\n"); } void -PC::clearPciInt(int line) +Pc::clearPciInt(int line) { panic("Need implementation\n"); } Addr -PC::pciToDma(Addr pciAddr) const +Pc::pciToDma(Addr pciAddr) const { panic("Need implementation\n"); M5_DUMMY_RETURN @@ -111,7 +111,7 @@ PC::pciToDma(Addr pciAddr) const Addr -PC::calcConfigAddr(int bus, int dev, int func) +Pc::calcConfigAddr(int bus, int dev, int func) { assert(func < 8); assert(dev < 32); @@ -119,8 +119,8 @@ PC::calcConfigAddr(int bus, int dev, int func) return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11)); } -PC * -PCParams::create() +Pc * +PcParams::create() { - return new PC(this); + return new Pc(this); } diff --git a/src/dev/x86/pc.hh b/src/dev/x86/pc.hh index 418a2e830..21055a566 100644 --- a/src/dev/x86/pc.hh +++ b/src/dev/x86/pc.hh @@ -38,13 +38,13 @@ #define __DEV_PC_HH__ #include "dev/platform.hh" -#include "params/PC.hh" +#include "params/Pc.hh" class IdeController; class System; class SouthBridge; -class PC : public Platform +class Pc : public Platform { public: /** Pointer to the system */ @@ -52,14 +52,14 @@ class PC : public Platform SouthBridge *southBridge; public: - typedef PCParams Params; + typedef PcParams Params; /** * Do platform initialization stuff */ void init(); - PC(const Params *p); + Pc(const Params *p); /** * Return the interrupting frequency to AlphaAccess diff --git a/src/dev/x86/south_bridge.cc b/src/dev/x86/south_bridge.cc index 3f68fee18..d366de4ad 100644 --- a/src/dev/x86/south_bridge.cc +++ b/src/dev/x86/south_bridge.cc @@ -40,7 +40,7 @@ SouthBridge::SouthBridge(const Params *p) : SimObject(p), cmos(p->cmos), speaker(p->speaker) { // Let the platform know where we are - PC * pc = dynamic_cast(platform); + Pc * pc = dynamic_cast(platform); assert(pc); pc->southBridge = this; } -- cgit v1.2.3