From c2d2ea99e3efe13bc50d410e2eeae9dd6757e57f Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Thu, 22 Mar 2012 06:36:27 -0400 Subject: MEM: Split SimpleTimingPort into PacketQueue and ports This patch decouples the queueing and the port interactions to simplify the introduction of the master and slave ports. By separating the queueing functionality from the port itself, it becomes much easier to distinguish between master and slave ports, and still retain the queueing ability for both (without code duplication). As part of the split into a PacketQueue and a port, there is now also a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The QueuedPort is useful for ports that want to leave the packet transmission of outgoing packets to the queue and is used by both master and slave ports. The SimpleTimingPort inherits from the QueuedPort and adds the implemention of recvTiming and recvFunctional through recvAtomic. The PioPort and MessagePort are cleaned up as part of the changes. --HG-- rename : src/mem/tport.cc => src/mem/packet_queue.cc rename : src/mem/tport.hh => src/mem/packet_queue.hh --- src/dev/x86/intdev.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/dev/x86') diff --git a/src/dev/x86/intdev.cc b/src/dev/x86/intdev.cc index bcfab5fe4..0d038b93d 100644 --- a/src/dev/x86/intdev.cc +++ b/src/dev/x86/intdev.cc @@ -50,7 +50,7 @@ X86ISA::IntDev::IntPort::sendMessage(ApicList apics, TriggerIntMessage message, for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) { PacketPtr pkt = buildIntRequest(*apicIt, message); if (timing) { - schedSendTiming(pkt, curTick() + latency); + queue.schedSendTiming(pkt, curTick() + latency); // The target handles cleaning up the packet in timing mode. } else { // ignore the latency involved in the atomic transaction -- cgit v1.2.3